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AM79C32A 데이터시트(PDF) 7 Page - Advanced Micro Devices |
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AM79C32A 데이터시트(HTML) 7 Page - Advanced Micro Devices |
7 / 101 page Am79C30A/32A Data Sheet 7 RD Read (Input) The active Low read signal is conditioned by CS and in- dicates that internal information is to be transferred onto the data bus. A number of internal registers are user accessible. The contents of the accessed register are transferred onto the data bus after the High to Low transition of the RD input. WR Write (Input) The active Low write signal is conditioned by CS and indicates that external information on the data bus is to be transferred to an internal register. The contents of the data bus are loaded on the Low to High transition of the WR input. Oscillator (OSC) MCLK Master Clock (Output) The MCLK output is available for use as the system clock for the microprocessor. MCLK is derived from the 12.288-MHz crystal via a programmable divider in the Am79C30A/32A which provides the following MCLK output frequencies: 12.288, 6.144, 4.096, 3.072, 1.536, 0.768, and 0.384 MHz. XTAL1, XTAL2 External Crystal (Output, Input) XTAL1 and XTAL2 are connected to an external parallel resonant crystal for the on-chip oscillator. XTAL2 can also be connected to an external source instead of a crystal, in which case XTAL1 should be left discon- nected. The frequency must be 12.288 MHz, ± 80 ppm. Peripheral Port (PP) SBIN Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBIN operates as an input for serial data. When the Pe- ripheral Port is programmed to IOM-2 mode, SBIN functions as the data input except in the special case of IOM-2 Slave mode, when it becomes an open-drain output during part or all of the IOM-2 frame, or when deactivated. SBOUT Serial Data (Input/Output) When the Peripheral Port is programmed to SBP mode, SBOUT operates as an output for serial data. When the Peripheral Port is programmed to IOM-2 mode, SBOUT functions as the data output except in the special case of IOM-2 Slave mode when it becomes an input during part or all of the IOM-2 frame. SCLK Serial Data Clock (Input/Output) When the PP is programmed to SBP mode, SCLK out- puts a 192-kHz data clock, which may be inverted under software control. When the PP is programmed to IOM-2 Master mode, SCLK outputs a 1.536-MHz 2X data clock. In IOM-2 Slave mode, SCLK functions as the clock input. The SCLK pin defaults to a high-imped- ance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. SFS Serial Frame Sync (Input/Output) In SBP mode, SFS outputs an 8-kHz frame synchroni- zation signal. SFS is an output in IOM-2 Master mode, and an input in IOM-2 Slave mode. As an output, SFS is active for 8-bit periods. The SFS pin defaults to a high-impedance state upon reset, but becomes active after any MUX connection is made or if the PP is pro- grammed to IOM-2 Master mode. For SBP mode, the active signal state is Low during Idle and 8 kHz in Ac- tive Data Only and Active Voice and Data modes. BCL/CH2STRB Bit Clock/SBP Channel 2 Strobe (Output, Three-state) In SBP mode, this pin provides a strobe during the 8-bit times of the second 64-kbit/s data channel. In IOM-2 Master mode, this pin provides a 768-kHz bit clock to aid in the connection of non-IOM-2 devices to the port. In IOM-2 Slave mode, this pin is high-impedance. Power Supply Pins PLCC/TQFP Packages AVCC +5-V analog power supply, ±5% AVSS Analog ground DVSS Digital ground DVCC +5-V digital power supply, ±5% Note: For best performance, decoupling capacitors should be in- stalled between VCC and VSS as close to the chip as possible. Do not use separate supplies for analog and digital power and ground connections. |
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