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AM79C982 데이터시트(PDF) 11 Page - Advanced Micro Devices |
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AM79C982 데이터시트(HTML) 11 Page - Advanced Micro Devices |
11 / 26 page AMD PRELIMINARY 1–13 Am79C982 that port’s transmitter has been inactive for more than 8 to 17 ms. Conversely, if a TP port does not receive any data packets or Link Test pulses for more than 65 to 132 ms and the Link Test function is enabled for that port then that port will enter link fail state. A port in link fail state will be disabled by the bIMR chip (repeater transmit and receive functions disabled) until it receives either four consecutive Link Test pulses or a data pack- et. The Link Test receive function itself can be disabled via the bIMR chip management port on a port-by-port basis to allow the bIMR device to interoperate with pre-10BASE-T twisted pair networks that do not imple- ment the Link Test function. This interoperability is pos- sible because the bIMR device will not allow the TP port to enter link fail state, even if no Link Test pulses or data packets are being received. Note however that the bIMR chip will always transmit Link Test pulses to all TP ports regardless of whether or not the port is enabled, parti- tioned, in link fail state, or has its Link Test receive func- tion disabled. Polarity Reversal The TP ports have the optional (programmable) ability to invert (correct) the polarity of the received data if the TP port senses that the received data packet waveform polarity is reversed due to a wiring error. This receive circuitry polarity correction allows subsequent packets to be repeated with correct polarity. This function is exe- cuted once following reset or link fail, and has a pro- grammable enable/disable option on a port-by-port basis. This function is disabled upon reset and can be enabled via the bIMR chip Management Port. Reset The bIMR device enters reset state when the RST pin is driven LOW. After the initial application of power, the RST pin must be held LOW for a minimum of 150 µs (3000 X1 clock cycles). If the RST pin is subsequently asserted while power is maintained to the bIMR device, a reset duration of only 4 µs is required. The bIMR chip continues to be in the reset state for 10 X1 clocks (0.5 µs) following the rising edge of RST. During reset, the output signals are placed in their inactive states. This means that all analog signals are placed in their idle states, bidirectional signals are not driven, active LOW signals are driven HIGH, and all active HIGH signals and the STR pin are driven LOW. An internal circuit ensures that a minimum reset pulse is generated for all internal circuits. For a RST input with a slow rising edge, the input buffer threshold may be crossed several times due to ripple on the input waveform. In a multiple bIMR chip repeater the RST signal should be applied simultaneously to all bIMR devices and should be synchronized to the external X1 clock. Reset synchronization is also required when accessing the PAM (Port Activity Monitor). The SI signal should be held HIGH for at least 500 ns fol- lowing the rising edge of RST. Table 1 summarizes the state of the bIMR chip following reset. Table 1. bIMR Chip After Reset Function State After Reset Pull Up/Pull Down Active LOW outputs HIGH No Active HIGH outputs LOW No SO Output HIGH No DAT, JAM HI-IMPEDANCE Either STR LOW No Transmitters (TP and AUI) IDLE No Receivers (TP and AUI) ENABLED Terminated AUI Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A TP Port Partitioning/Reconnection Algorithm STANDARD ALGORITHM N/A Link Test Function for TP Ports ENABLED, TP PORTS IN LINK FAIL N/A Automatic Receiver Polarity Reversal Function DISABLED N/A |
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