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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD7243SQ 데이터시트(PDF) 6 Page - List of Unclassifed Manufacturers |
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AD7243SQ 데이터시트(HTML) 6 Page - List of Unclassifed Manufacturers |
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6 / 12 page  STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93204 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55 °C ≤ T A ≤+125°C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Voltage output settling time, positive full scale 6/ change tPS See 4.4.1c 4 01 12 µs Voltage output settling time, negative full scale 6/ change tNS VSS = -12 V to -15 V See 4.4.1c 4 01 10 µs SCLK cycle time 7/ 8/ t1 SCLK mark/space ratio range is 40/60 to 60/40, see figure 2 9, 10, 11 01 200 ns SYNC to SCLK falling edge setup time 7/ 8/ t2 See figure 2 9, 10, 11 01 50 ns SYNC to SCLK hold time t3 See figure 2 9 01 120 ns 7/ 8/ 10, 11 190 Data setup time 7/ 8/ t4 See figure 2 9, 10, 11 01 10 ns Data hold time 7/ 8/ t4 See figure 2 9, 10, 11 01 100 ns SYNC high to LDAC low 7/ 8/ t6 See figure 2 9, 10, 11 01 0 ns LDAC pulse width 7/ 8/ t7 See figure 2 9, 10, 11 01 50 ns LDAC high to SYNC low 7/ 8/ t6 See figure 2 9, 10, 11 01 0 ns CLR pulse width 7/ 8/ t9 See figure 2 9, 10, 11 01 75 ns SCLK falling edge to SD0 t10 SD0 load capacitance is no 9 01 120 ns Valid 7/ 8/ 9/ Greater than 50 pF 10, 11 180 1/ VDD = +11.4 V to +15.75 V. VSS = 0 V or –11.4 V to –15.75 V. AGND = DGND = 0 V. REFIN = +5 V. RL = 2 kΩ. CL = 100 pF to AGND. Parts are guaranteed over this supply range. Individual tests are performed with known worst case supply conditions. Unless otherwise noted VDD = +11.4 V and VSS = –11.4 V 2/ VDD = 14.25 V, VSS = 0 V on 10 V range. VDD = 14.25 V, VSS = –14.25 V on 10 V range. VDD = 11.4 V, VSS = –11.4 V on 5 V range 3/ Measured with respect to REFIN and includes unipolar and bipolar offset error. 4/ REFIN is connected to REFOUT for all tests except RIN. 5/ Analog output voltage ranges are guaranteed by passing of DC accuracy tests. 6/ 0 V to +10 V output range is available only with VDD ≥ +14.25 V. 7/ All input signals are specified with tr = tf = 5 ns (10% to 90% 0f 5 V) and timed from a voltage level of 1.6 V. 8/ Subgroups 10 and 11 are measured only at initial design characterization and after process or design changes which might affect this parameter. This limit is guaranteed even though it is not tested. 9/ t10 measured only at initial design characterization and after process or design changes which might affect this parameter. This limit is guaranteed even though it is not tested. |
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