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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AMC010CFLKA 데이터시트(PDF) 5 Page - Advanced Micro Devices |
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AMC010CFLKA 데이터시트(HTML) 5 Page - Advanced Micro Devices |
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5 / 42 page  5/4/98 AmC0XXCFLKA 5 PIN DESCRIPTION A0–A23 Address Inputs These inputs are internally latched during write cycles. BVD1, BVD2 Battery Voltage Detect Internally pulled-up. CD1, CD2 Card Detect When card detect 1 and 2 = ground the system detects the card. CE1, CE2 Card Enable This input is active low. The memory card is deselected and power consumption is reduced to standby levels when CE is high. CE activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers segment decoders, and associated memory devices. D0–D15 Data Input/Output Data inputs are internally latched on write cycles. Data outputs during read cycles. Data pins are active high. When the memory card is deselected or the outputs are disabled the outputs float to tristate. GND Ground NC No Connect Corresponding pin is not connected internally to the die. OE Output Enable This input is active low and enables the data buffers through the card outputs during read cycles. REG Attribute Memory Select This input is active low and enables reading the CIS from the EEPROM. VCC PC Card Power Supply For device operation (5.0 V ± 5%). WE Write Enable This input is active low and controls the write function of the command register to the memory array. The target address is latched on the falling edge of the WE pulse and the appropriate data is latched on the rising edge of the pulse. WP Write Protect This output is active high and disables all card write operations. MEMORY CARD OPERATIONS The “C” series Flash Memory Card is organized as an array of individual devices. Each device is 512K bytes in size with eight 64K byte sectors. Although the ad- dress space is continuous each physical device defines a logical address segment size. Byte-wide erase operations could be performed in four ways: s In increments of the segment size s In increments of the sectors in individual segments s All eight sectors in parallel within individual segments s Selected sectors of the eight sectors in parallel within individual segments Multiple segments may be erased concurrently when additional ICC current is supplied to the device. Once a memory sector or memory segment is erased any ad- dress location may be programmed. Flash technology allows any logical “1” data bit to be programmed to a logical “0”. The only way to reset bits to a logical “1” is to erase the entire memory sector of 64K bytes or memory segment of 512K bytes. Erase operations are the only operations that work on entire memory sectors or memory segments. All other operations such as word-wide programming are not af- fected by the physical memory segments. The common memory space data contents are altered in a similar manner as writing to individual Flash mem- ory devices. On-card address and data buffers activate the appropriate Flash device in the memory array. Each device internally latches address and data during write cycles. Refer to Table 1. Attribute memory is a separately accessed card mem- ory space. The register memory space is active when the REG pin is driven low. The Card Information Struc- ture (CIS) describes the capabilities and specification of a card. The CIS is stored in the attribute memory space beginning at address 00000H. The “C” series cards contain a separate 512 byte EEPROM memory for the Card Information Structure. D0–D7 are active during attribute memory accesses. D8–D15 should be ignored. Odd order bytes present invalid data. Refer to Table 2. |
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