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74AUP1G32GN 데이터시트(PDF) 8 Page - NXP Semiconductors

부품명 74AUP1G32GN
상세설명  Low-power 2-input OR-gate
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74AUP1G32GN 데이터시트(HTML) 8 Page - NXP Semiconductors

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74AUP1G32
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 8 July 2013
8 of 21
NXP Semiconductors
74AUP1G32
Low-power 2-input OR-gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 25 C; CL = 5 pF
tpd
propagation delay
A, B to Y; see Figure 8
[2]
VCC = 0.8 V
-
16.8
-
ns
VCC = 1.1 V to 1.3 V
2.4
5.1
10.9
ns
VCC = 1.4 V to 1.6 V
1.6
3.6
6.6
ns
VCC = 1.65 V to 1.95 V
1.4
3.0
5.2
ns
VCC = 2.3 V to 2.7 V
1.1
2.4
3.9
ns
VCC = 3.0 V to 3.6 V
1.0
2.1
3.5
ns
Tamb = 25 C; CL = 10 pF
tpd
propagation delay
A, B to Y; see Figure 8
[2]
VCC = 0.8 V
-
20.3
-
ns
VCC = 1.1 V to 1.3 V
2.3
5.9
12.7
ns
VCC = 1.4 V to 1.6 V
1.9
4.2
7.7
ns
VCC = 1.65 V to 1.95 V
1.7
3.5
6.0
ns
VCC = 2.3 V to 2.7 V
1.4
2.9
4.6
ns
VCC = 3.0 V to 3.6 V
1.3
2.7
4.3
ns
Tamb = 25 C; CL = 15 pF
tpd
propagation delay
A, B to Y; see Figure 8
[2]
VCC = 0.8 V
-
23.8
-
ns
VCC = 1.1 V to 1.3 V
3.3
6.7
14.3
ns
VCC = 1.4 V to 1.6 V
2.3
4.8
8.6
ns
VCC = 1.65 V to 1.95 V
2.0
4.0
6.7
ns
VCC = 2.3 V to 2.7 V
1.7
3.3
5.3
ns
VCC = 3.0 V to 3.6 V
1.5
3.1
4.9
ns
Tamb = 25 C; CL = 30 pF
tpd
propagation delay
A, B to Y; see Figure 8
[2]
VCC = 0.8 V
-
34.1
-
ns
VCC = 1.1 V to 1.3 V
4.5
9.0
19.1
ns
VCC = 1.4 V to 1.6 V
3.4
6.3
11.3
ns
VCC = 1.65 V to 1.95 V
2.6
5.3
8.9
ns
VCC = 2.3 V to 2.7 V
2.3
4.4
7.0
ns
VCC = 3.0 V to 3.6 V
2.2
4.2
6.4
ns


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