전자부품 데이터시트 검색엔진 |
|
74LVC2G00GM 데이터시트(PDF) 1 Page - NXP Semiconductors |
|
74LVC2G00GM 데이터시트(HTML) 1 Page - NXP Semiconductors |
1 / 20 page 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity 24 mA output drive (V CC =3.0 V) CMOS low power consumption Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto +85 C and 40 Cto+125 C 74LVC2G00 Dual 2-input NAND gate Rev. 12 — 8 April 2013 Product data sheet |
유사한 부품 번호 - 74LVC2G00GM |
|
유사한 설명 - 74LVC2G00GM |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |