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LM2748 데이터시트(PDF) 10 Page - Texas Instruments |
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LM2748 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 37 page LM2745, LM2748 SNOSAL2E – APRIL 2005 – REVISED APRIL 2013 www.ti.com It is recommended to choose an AC coupling capacitance in the range of 50 pF to 100 pF. Exceeding the recommended capacitance may inject excessive energy through the internal clamping diode structure present on the FREQ/SYNC pin. The typical trip level of the synchronization pin is 1.5V. To ensure proper synchronization and to avoid damaging the IC, the peak-to-peak value (amplitude) should be between 2.5V and VCC. The minimum width of this pulse must be greater than 100 ns, and it's maximum width must be 100ns less than the period of the switching cycle. The external clock synchronization process begins once the LM2745 is enabled and an external clock signal is detected. During the external clock synchronization process the internal clock initially switches at approximately 1.5 MHz and decreases until it has matched the external clock’s frequency. The lock-in period is approximately 30 µs if the external clock is switching at 1 MHz, and about 100 µs if the external clock is at 200 kHz. When there is no clock signal present, the LM2745 enters into fixed-frequency mode and begins switching at the frequency set by the RFADJ resistor. If the external clock signal is removed after frequency synchronization, the LM2745 will enter fixed-frequency mode within two clock cycles. If the external clock is removed within the 30 µs lock-in period, the LM2745 will re-enter fixed-frequency mode within two internal clock cycles after the lock-in period. OUTPUT PRE-BIAS STARTUP If there is a pre-biased load on the output of the LM2745/8 during startup, the IC will disable switching of the low- side MOSFET and monitor the SW node voltage during the off-time of the high-side MOSFET. There is no load current sensing while in pre-bias mode because the low-side MOSFET never turns on. The IC will remain in this pre-bias mode until it sees the SW node stays below 0V during the entire high-side MOSFET's off-time. Once it is determined that the SW node remained below 0V during the high-side off-time, the low-side MOSFET begins switching during the next switching cycle. Figure 18 shows the SW node, HG, and LG signals during pre-bias startup. The pre-biased output voltage should not exceed VCC + VGS of the external High-Side MOSFET to ensure that the High-Side MOSFET will be able to switch during startup. Figure 18. Output Pre-Bias Mode Waveforms TRACKING A VOLTAGE LEVEL The LM2745/8 can track the output of a master power supply during soft-start by connecting a resistor divider to the SS/TRACK pin. In this way, the output voltage slew rate of the LM2745/8 will be controlled by the master supply for loads that require precise sequencing. When the tracking function is used no soft-start capacitor should be connected to the SS/TRACK pin. However in all other cases, a CSS value of at least 1 nF between the soft-start pin and ground should be used. 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM2745 LM2748 |
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