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AD8111-EB 데이터시트(PDF) 8 Page - Analog Devices |
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AD8111-EB 데이터시트(HTML) 8 Page - Analog Devices |
8 / 29 page REV. A AD8110/AD8111 –7– PIN FUNCTION DESCRIPTIONS Pin Name Pin Numbers Pin Description INxx 66, 68, 70, 72, 74, 76, 78, Analog Inputs; xx = Channel Numbers 00 Through 15. 1, 3, 5, 7, 9, 11, 13, 15, 64 DATA IN 57 Serial Data Input, TTL Compatible. CLK 58 Clock, TTL Compatible. Falling Edge Triggered. DATA OUT 59 Serial Data Out, TTL Compatible. UPDATE 56 Enable (Transparent) “Low.” Allows serial register to connect directly to switch matrix. Data latched when “High.” RESET 61 Disable Outputs, Active “Low.” CE 60 Chip Enable, Enable “Low.” Must be “low” to clock in and latch data. SER/PAR 55 Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected. OUTyy 41, 38, 35, 32, 29, 26, 23, 20 Analog Outputs yy = Channel Numbers 00 Through 07. AGND 2, 4, 6, 8, 10, 12, 14, 16, 46 Analog Ground for Inputs and Switch Matrix. 65, 67, 69, 71, 73, 75, 77 DVCC 63, 79 5 V for Digital Circuitry. DGND 62, 80 Ground for Digital Circuitry. AVEE 17, 45 –5 V for Inputs and Switch Matrix. AVCC 18, 44 +5 V for Inputs and Switch Matrix. AGNDxx 42, 39, 36, 33, 30, 27, 24, 21 Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected. AVCCxx/yy 43, 37, 31, 25, 22, 19 +5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. AVEExx/yy 40, 34, 28, 22 –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. A0 54 Parallel Data Input, TTL Compatible (Output Select LSB). A1 53 Parallel Data Input, TTL Compatible (Output Select). A2 52 Parallel Data Input, TTL Compatible (Output Select MSB). D0 51 Parallel Data Input, TTL Compatible (Input Select LSB). D1 50 Parallel Data Input, TTL Compatible (Input Select). D2 49 Parallel Data Input, TTL Compatible (Input Select). D3 48 Parallel Data Input, TTL Compatible (Input Select MSB). D4 47 Parallel Data Input, TTL Compatible (Output Enable). ESD ESD INPUT VCC AVEE ESD ESD OUTPUT VCC AVEE 1k (AD8111 ONLY) ESD ESD RESET VCC 20k DGND ESD ESD INPUT VCC DGND ESD ESD OUTPUT VCC 2k DGND Figure 5. I/O Schematics a. Analog Input b. Analog Output c. Reset Input d. Logic Input e. Logic Output |
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