전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD7810YR 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD7810YR
상세설명  2.7 V to 5.5 V, 2.3 s, 10-Bit ADC in 8-Lead microSOIC/DIP
Download  11 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD7810YR 데이터시트(HTML) 6 Page - Analog Devices

Back Button AD7810YR Datasheet HTML 2Page - Analog Devices AD7810YR Datasheet HTML 3Page - Analog Devices AD7810YR Datasheet HTML 4Page - Analog Devices AD7810YR Datasheet HTML 5Page - Analog Devices AD7810YR Datasheet HTML 6Page - Analog Devices AD7810YR Datasheet HTML 7Page - Analog Devices AD7810YR Datasheet HTML 8Page - Analog Devices AD7810YR Datasheet HTML 9Page - Analog Devices AD7810YR Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 11 page
background image
AD7810
–6–
REV. B
CIRCUIT DESCRIPTION
Converter Operation
The AD7810 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Fig-
ures 4 and 5 below show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A; the comparator is held in a
balanced condition; and the sampling capacitor acquires the
signal on VIN+.
VDD/3
VIN+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
ACQUISITION
PHASE
SW2
A
SW1
B
VIN
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to Position B, causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 11 shows the ADC transfer function.
VDD/3
VIN+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW2
A
SW1
B
VIN
Figure 5. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7810. The
serial interface is implemented using two wires; the rising edge
of CONVST enables the serial interface—see Serial Interface
section for more details. VREF is connected to a well decoupled
VDD pin to provide an analog input range of 0 V to VDD. When
VDD is first connected, the AD7810 powers up in a low current
mode, i.e., power-down. A rising edge on the CONVST input
will cause the part to power up—see Operating Modes. If power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power perfor-
mance. See Power vs. Throughput Rate section of the data sheet.
DOUT
SCLK
VREF
AGND
VDD
VIN+
VIN
CONVST
SUPPLY
2.7V TO 5.5V
0V TO VREF
INPUT
AD7810
0.1 F
10 F
TWO WIRE
SERIAL
INTERFACE
C/ P
Figure 6. Typical Connection Diagram
Analog Input
Figure 7 shows an equivalent circuit of the analog input struc-
ture of the AD7810. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125
Ω. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
VDD
VIN+
C1
3.5pF
R1
125
VDD/3
D2
D1
C2
4pF
CONVERT PHASE – SWITCH OPEN
ACQUISITION PHASE – SWITCH CLOSED
Figure 7. Equivalent Analog Input Circuit
The analog input of the AD7810 is made up of a pseudo differ-
ential pair. VIN+ pseudo differential with respect to VIN–. The
signal is applied to VIN+, but in the pseudo differential scheme
the sampling capacitor is connected to VIN– during conversion
(see Figure 8). This input scheme can be used to remove offsets
that exist in a system. For example, if a system had an offset of
0.5 V, the offset could be applied to VIN– and the signal applied
to VIN+. This has the effect of offsetting the input span by 0.5 V.
It is only possible to offset the input span when the reference
voltage (VREF) is less than VDD – VOFFSET.
VDD/3
VIN+
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW2
VIN
CHARGE
REDISTRIBUTION
DAC
VOFFSET
VIN(+)
VOFFSET
Figure 8. Pseudo Differential Input Scheme


유사한 부품 번호 - AD7810YR

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7810YR AD-AD7810YR Datasheet
142Kb / 11P
   2.7 V to 5.5 V, 2 us, 10-Bit ADC in 8-Lead microSOIC/DIP
REV. A
AD7810YR AD-AD7810YR Datasheet
186Kb / 12P
   ADC in 8-Lead microSOIC/DIP
AD7810YRM AD-AD7810YRM Datasheet
142Kb / 11P
   2.7 V to 5.5 V, 2 us, 10-Bit ADC in 8-Lead microSOIC/DIP
REV. A
AD7810YRM AD-AD7810YRM Datasheet
186Kb / 12P
   ADC in 8-Lead microSOIC/DIP
More results

유사한 설명 - AD7810YR

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7810 AD-AD7810_15 Datasheet
160Kb / 11P
   2.7 V to 5.5 V, 2.3s, 10-Bit ADC in 8-Lead microSOIC/DIP
REV. B
AD7823YRM-REEL AD-AD7823YRM-REEL Datasheet
146Kb / 11P
   2.7 V to 5.5 V, 5s, 8-Bit ADC in 8-Lead microSOIC/DIP
REV. C
AD7823 AD-AD7823_15 Datasheet
156Kb / 11P
   2.7 V to 5.5 V, 5s, 8-Bit ADC in 8-Lead microSOIC/DIP
REV. C
AD7810 AD-AD7810 Datasheet
142Kb / 11P
   2.7 V to 5.5 V, 2 us, 10-Bit ADC in 8-Lead microSOIC/DIP
REV. A
AD7823 AD-AD7823 Datasheet
155Kb / 11P
   2.7 V to 5.5 V, 4.5 us, 8-Bit ADC in 8-Lead microSOIC/DIP
REV. B
AD7896ANZ AD-AD7896ANZ Datasheet
1Mb / 15P
   2.7 V to 5.5 V, 12-Bit, 8 s ADC in 8-Lead SOIC/PDIP
REV. D
AD7896JRZ AD-AD7896JRZ Datasheet
1Mb / 15P
   2.7 V to 5.5 V, 12-Bit, 8 s ADC in 8-Lead SOIC/PDIP
REV. D
AD7823 AD-AD7823_17 Datasheet
187Kb / 12P
   ADC in 8-Lead microSOIC/DIP
AD7896 AD-AD7896 Datasheet
367Kb / 12P
   2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIP
REV. B
AD7896 AD-AD7896_17 Datasheet
1Mb / 16P
   2.7 V to 5.5 V, 12-Bit ADC in 8-Lead SOIC/PDIP
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com