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FM31256-G 데이터시트(PDF) 8 Page - Cypress Semiconductor |
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FM31256-G 데이터시트(HTML) 8 Page - Cypress Semiconductor |
8 / 27 page FM31256/3164 Processor Companion Document Number: 001-86391 Rev. *B Page 8 of 27 32.768 kHz crystal Oscillator Clock Divider Update Logic 512 Hz W R Seconds 7 bits Minutes 7 bits Hours 6 bits Date 6 bits Months 5 bits Years 8 bits CF Days 3 bits User Interface Registers 1 Hz /OSCEN Figure 9. Real-Time Clock Core Block Diagram Calibration When the CAL bit in a register 00h is set to 1, the clock enters calibration mode. In calibration mode, the CAL/PFO output pin is dedicated to the calibration function and the power fail output is temporarily unavailable. Calibration operates by applying a digital correction to the counter based on the frequency error. In this mode, the CAL/PFO pin is driven with a 512 Hz (nominal) square wave. Any measured deviation from 512 Hz translates into a timekeeping error. The user converts the measured error in ppm and writes the appropriate correction value to the calibration register. The correction factors are listed in the table below. Positive ppm errors require a negative adjustment that removes pulses. Negative ppm errors require a positive correction that adds pulses. Positive ppm adjustments have the CALS (sign) bit set to 1, where as negative ppm adjustments have CALS = 0. After calibration, the clock will have a maximum error of 2.17 ppm or 0.09 minutes per month at the calibrated temperature. The calibration setting is stored in FRAM so is not lost should the backup source fail. It is accessed with bits CAL.4-0 in register 01h. This value only can be written when the CAL bit is set to a 1. To exit the calibration mode, the user must clear the CAL bit to a 0. When the CAL bit is 0, the CAL/PFO pin will revert to the power fail output function. Crystal Oscillator The crystal oscillator is designed to use a 6pF crystal without the need for external components, such as loading capacitors. The FM31xx device has built-in loading capacitors that match the crystal. If a 32.768kHz crystal is not used, an external oscillator may be connected to the FM31xx. Apply the oscillator to the X1 pin. Its high and low voltage levels can be driven rail -to-rail or amplitudes as low as approximately 500mV p -p. To ensure proper operation, a DC bias must be applied to the X2 pin. It should be centered between the high and low levels on the X1 pin. This can be accomplished with a voltage divider. Figure 10. External Oscillator In the example, R1 and R2 are chosen such that the X2 voltage is centered around the X1 oscillator drive levels. If you wish to avoid the DC current, you may choose to drive X1 with an external clock and X2 with an inverted clock using a CMOS inverter. Layout Requirements The X1 and X2 crystal pins employ very high impedance circuits and the oscillator connected to these pins can be upset by noise or extra loading. To reduce RTC clock errors from signal switching noise, a guard ring must be placed around these pads and the guard ring grounded. SDA and SCL traces should be routed away from the X1/X2 pads. The X1 and X2 trace lengths should be less than 5 mm. The use of a ground plane on the backside or inner board layer is preferred. See layout example. Red is the top layer, green is the bottom layer. |
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