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FAN23SV04TMPX 데이터시트(PDF) 10 Page - Fairchild Semiconductor |
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FAN23SV04TMPX 데이터시트(HTML) 10 Page - Fairchild Semiconductor |
10 / 17 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN23SV04T • Rev. 1.0.1 10 Circuit Operation The FAN23SV04T uses a constant-on-time modulation architecture with a VIN feed-forward input to accommodate a wide VIN range. This method provides fixed switching frequency (fSW) operation when the inductor operates in Continuous Conduction Mode (CCM). Additional benefits include excellent line and load transient response, cycle-by-cycle current limiting, and elimination of loop compensation requirements. At the beginning of each cycle, FAN23SV04T turns on the high-side MOSFET (HS) for a fixed duration (tON). At the end of tON, HS turns off for a duration (tOFF) determined by the operating conditions. Once the FB voltage (VFB) falls below the reference voltage (VREF), a new switching cycle begins. The modulator provides a minimum off-time (tOFF-MIN) of 250 ns to provide a guaranteed interval for low-side MOSFET (LS) current sensing and PFM operation. tOFF- MIN provides stability against multiple pulsing and limits maximum switching frequency during transient events. Enable The enable pin can be driven with an external logic signal, connected to a resistive divider from PVIN/Vin to ground to create an Under-Voltage Lockout (UVLO) based on the PVIN/VIN supply, or connected to PVIN/VIN through a single resistor to auto-enable while operating within the EN pin internal clamp current sink capability. The EN pin can be directly driven by logic voltages of 5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5 V logic, a small current flows into the pin when the EN pin voltage exceeds the internal clamp voltage of 4.3 V. To eliminate clamp current flowing into the EN pin use a voltage divider to limit the EN pin voltage to < 4 V. To implement the UVLO function based on PVIN/VIN voltage level, select values for R7 and R8 in Figure 1 such that the tap point reaches 1.26 V when VIN reaches the desired startup level using the following equation: ����7=����8�������������,��������������������,��������−1� (1) where VIN,on is the input voltage for startup and VEN,on is the EN pin rising threshold of 1.26 V. With R8 selected as 10 kΩ, and VIN,on=9 V the value of R7 is 61.9 kΩ. The EN pin can be pulled high with a single resistor connected from VIN to the EN pin. With VIN > 5.5V a series resistor is required to limit the current flow into the EN pin clamp to less than 24 µA to keep the internal clamp within normal operating range. The resistor value can be calculated from the following equation: ������������>������������,������������−������������,��������������������,������������ 22µ���� (2) Constant On-Time Modulation The FAN23SV04T uses a constant on-time modulation technique, in which the HS MOSFET is turned on for a fixed time, set by the modulator, in response to the input voltage and the frequency-setting resistor. This on-time is proportional to the desired output voltage, divided by the input voltage. With this proportionality, the frequency is essentially constant over the load range where inductor current is continuous. For a buck converter in Continuous-Conduction Mode (CCM), the switching frequency fSW is expressed as: ������������= ����������������������������∙������������ (3) The on-time generator sets the on-time (tON) for the high-side MOSFET, which results in the switching frequency of the regulator during steady-state operation. To maintain a relatively constant switching frequency over a wide range of input conditions, the input voltage information is fed into the on-time generator. tON is determined by: ������������=��������������������������������∙2���� (4) where ItON is: ����������������=110∙ �������������������������������� (5) where RFREQ is the frequency-setting resistor described in the Setting Switching Frequency section; CtON is the internal 2.2 pF capacitor; and ItON is the VIN feed-forward current that generates the on-time. The FAN23SV04T implements open-circuit detection on the FREQ pin to protect the output from an infinitely long on-time. In the event the FREQ pin is left floating, switching of the regulator is disabled. The FAN23SV04T is designed for a VIN input range 7 to 15 V and fSW from 200 kHz to 1.5 MHz, resulting in an ItON ratio of 1 to 16. As the ratio of VOUT to VIN increases, tOFF,min introduces a limit on the maximum switching frequency as calculated in the following equation, where the factor 1.2 is included in the denominator to provide some headroom for transient operation: ������������<��1− ����������������������������,������������� 1.2∙����������������,������������ (6) VDDQ This pin is connected to the VDDQ supply, which the FAN23SV04T must track during startup and produce an output (VTT) equal to half of VDDQ in steady-state conditions. To accomplish this, the VDDQ pin has an internal resistor divider to AGND that provides a reference voltage equal to VDDQ/2 at the positive input of the FB comparator. Soft-Start (SS) A conventional soft-start ramp is implemented to provide a controlled startup sequence of the output voltage. A current is generated on the SS pin to charge an external capacitor. The lesser of the voltage on the SS pin and the reference voltage is used for output regulation. |
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