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CS51033YN8 데이터시트(PDF) 5 Page - Cherry Semiconductor Corporation |
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CS51033YN8 데이터시트(HTML) 5 Page - Cherry Semiconductor Corporation |
5 / 8 page 5 Circuit Description: continued Applications Information Specifications VIN = 3.3V +/- 10% (i.e. 3.63V max., 2.97V min.) VOUT = 1.5V +/- 2% IOUT = 0.3A to 3A Output ripple voltage < 33mV. FSW = 200kHz. 1) Duty Cycle Estimates Since the maximum duty cycle, D, of the CS51033 is limited to 80% min. it is best to estimate the duty cycle for the vari- ous input conditions to see that the design will work over the complete operating range. The duty cycle for a buck regulator operating in a continu- ous conduction mode is given by: D = Where VSAT is Rdson × IOUT Max. In this case we can assume that VD = 0.6V and VSAT = 0.6V so the equation reduces to: VOUT + VD VIN - VSAT Designing a Power Supply with the CS51033 feedback to the VFB Comparator sets the GATE flip-flop dur- ing COSC ’s charge cycle. Once the GATE flip-flop is set, VGATE goes low and turns on the PFET. When VCS exceeds 2.4V, the CS charge sense comparator (A4) sets the VFB com- parator reference to 1.25V completing the startup cycle. Lossless Short Circuit Protection The CS51033 has “Lossless” short circuit protection since there is no current sense resistor required. When the voltage at the CS pin (the fault timing capacitor voltage ) reaches 2.5V, the fault timing circuitry is enabled. During normal operation the CS voltage is 2.6V. During a short circuit con- dition or a transient condition, the output voltage moves lower and the voltage at VFB drops. If VFB drops below 1.15V, the output of the fault comparator goes high and the CS51033 goes into a fast discharge mode. The fault timing capacitor, CS, discharges to 2.4V. If the VFB voltage is still below 1.15V when the CS pin reaches 2.4V, a valid fault con- dition has been detected. The slow discharge comparator output goes high and enables gate G5 which sets the slow discharge flip flop. The Vgate flip flop resets and the output switch is turned off. The fault timing capacitor is slowly dis- charged to 1.5V. The CS51033 then enters a normal startup routine. If the fault is still present when the fault timing capacitor voltage reaches 2.5V, the fast and slow discharge cycles repeat as shown in figure 2. If the VFB voltage is above 1.15V when CS reaches 2.4V a fault condition is not detected, normal operation resumes and CS charges back to 2.6V. This reduces the chance of erroneously detecting a load transient as a fault condition. Figure 2. Voltage on start capacitor (VGS ), the gate (VGATE ), and in the feedback loop (VFB), during startup, normal and fault conditions. Buck Regulator Operation Figure 3. Buck regulator block diagram. A block diagram of a typical buck regulator is shown in Figure 3. If we assume that the output transistor is initially off, and the system is in discontinuous operation, the induc- tor current IL is zero and the output voltage is at its nominal value. The current drawn by the load is supplied by the out- put capacitor CO . When the voltage across CO drops below the threshold established by the feedback resistors R1 and R2 and the reference voltage VREF, the power transistor Q1 switches on and current flows through the inductor to the output. The inductor current rises at a rate determined by (VIN-VOUT)/Load. The duty cycle (or “on” time) for the CS51033 is limited to 80%. If the output voltage remains higher than nominal during the entire COSC charge time, the Q1 does not turn on, skipping the pulse. CHARGE PUMP CIRCUIT (Refer to the CS51033 Application Diagram) An external charge pump circuit is necessary when the input voltage is below 5V to ensure that there is sufficient gate drive voltage for the external FET. When VIN is applied, capacitors C1 and C2 will be charged to a diodes drop below VIN via diodes D2 and D4, respectively. When the PFET turns on, its drain voltage will be approximately equal to VIN. Since the voltage across C1 can not change instanta- neously, D2 is reverse biased and the anode voltage rises to approximately 2*3.3V-VD2. C1 transfers some of its stored charge C2 via D3. After several cycles there is sufficient gate drive voltage. Control Feedback VIN L D1 R1 R2 RLOAD CO Q1 CIN 2.5V 0V FAULT NORMAL OPERATION START TSTART td1 td2 tFAULT tRESTART tFAULT S2 S2 S2 S3 S3 S3 S3 S1 S1 S1 2.6V 2.4V 1.5V 0V 1.25V 1.15V VCS VGATE VFB |
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