전자부품 데이터시트 검색엔진 |
|
CS5126XD8 데이터시트(PDF) 5 Page - Cherry Semiconductor Corporation |
|
CS5126XD8 데이터시트(HTML) 5 Page - Cherry Semiconductor Corporation |
5 / 10 page 5 Block Diagram G2 {2.65V} 2.90V V5REF GATE ÷ VFB ISENSE VCC 2.62 V/2.45V 1.91 V/1.83V REMOTE (SLEEP) COMP SS VCC UVLO COMP 7.7 V/7.275V LINE AMP (CS5124 ONLY) 2.9 R R 2.0V + SS COMP 275mV V V V V 1.32V + V {525mV} 275mV {125mV} 60mV V + + DRIVER 490mV VFB COMP PWM COMP 2ND ICOMP + - + LINE UVLO COMP RESET DOMAIN G6 4500Ω BIAS UVLO G1 V5REF F1 R Q S G7 1000Ω BLANKING 10µA V5REF V5REF V BLANK VCC V V TSHUT V F2 R Q S + - SS AMP + - V {85 mV/us} 170mV us {1/5} 1/10 G5 OSC RAMP ENABLE VCC VREF = 5V G3 VREFOK SYNC {CS5126 ONLY} DIS F3 R Q S SET DOMAIN SOFT START LATCH 150°C/125°C + Gnd + + + + + + - Theory of Operation Powering the IC VCC can be powered directly from a regulated supply and requires 500µA of start-up current. The CS5124/6 includes a line bias pin (BIAS) that can be used to control a series pass transistor for operation over a wide input volt- age. The BIAS pin will control the gate voltage of an N- channel MOSFET placed between VIN and VCC to regulate VCC at 8V. VCC and UVLO Pins The UVLO pin has three different modes; low power shut- down, Line UVLO, and normal operation. To illustrate how the UVLO pin works; assume that VIN, as shown in the application schematic, is ramped up starting at 0V with the UVLO pin open. The SS and ISENSE pins also start at 0V. While the UVLO is below 1.8V, the IC will remain in a low current sleep mode and the BIAS pin of the CS5124 is inter- nally clamped to a maximum of 15V. When the voltage on the UVLO pin rises to between 1.8V and 2.6V the reference for the VCC UVLO is enabled and VCC is regulated to 8V by the BIAS pin (CS5124 only), but the IC remains in a UVLO state and the output driver does not switch. When the UVLO pin exceeds 2.6V and the VCC pin exceeds 7.7V, the GATE pin is released from a low state and can begin switching based on the comparison of the ISENSE and VFB pins. The Soft Start capacitor begins charging from 0V at 10µA. As the capacitor charges, a buffered version of the capacitor voltage appears on the VFB pin and the VFB volt- age begins to rise. As VFB rises the duty cycle increases until the supply comes into regulation. Soft Start Soft Start is accomplished by clamping the VFB pin 1.32V below the SS pin during normal start up and during restart after a fault condition. When the CS5124/6 starts, the Soft Start capacitor is charged from a 10µA source from 0V to 4.9V. The VFB pin follows the Soft Start pin offset by –1.32V until the supply comes into regulation or until the Soft Start error amp is clamped at 2.9V (2.65V for the CS5126). During fault conditions the Soft Start capacitor is dis- charged at 10mA. Fault Conditions The CS5124/6 recognizes the following faults: UVLO off, Thermal Shutdown, VREF(OK), and Second Current Threshold. Once a fault is recognized, fault latch F2 is set and the IC immediately shuts down the output driver and discharges the Soft Start capacitor. Soft Start will begin only after all faults have been removed and the Soft Start capacitor has been discharged to less than 0.275V. Each fault will be explained in the following sections. |
유사한 부품 번호 - CS5126XD8 |
|
유사한 설명 - CS5126XD8 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |