전자부품 데이터시트 검색엔진 |
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CS4215 데이터시트(PDF) 5 Page - Cirrus Logic |
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CS4215 데이터시트(HTML) 5 Page - Cirrus Logic |
5 / 52 page SDIN SDOUT t nz t pd1 t hz t pd1 t s1 t h1 TS 1, Bit 7 TS 1, Bit 7 TS 1, Bit 6 SCLK t pd1 t pd1 t pd2 TSOUT t pd2 TS 8, Bit 0 TS 1, Bit 6 FSYNC out TSIN FSYNC in t s1 t h1 t h1 t s1 TS 8, Bit 0 t sckl t sckh t sckw SWITCHING CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1, VD2 = +5V, outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2) Parameter Symbol Min Typ Max Units SCLK period Master Mode, XCLK = 1 (Note 8) tsckw -1/(Fs*bpf) - s Slave Mode (XCLK = 0) tsckw 80 - - ns SCLK high time Slave Mode, XCLK = 0 (Note 9) tsckh 25 - - ns SCLK low time Slave Mode, XCLK = 0 (Note 9) tsckl 25 - - ns Input Setup Time ts1 15 - - ns Input Hold Time th1 10 - - ns Input Transition Time 10% to 90% points - - 10 ns Output delay tpd1 - - 28 ns SCLK to TSOUT tpd2 - - 30 ns Output to Hi-Z state Timeslot 8, bit 0 thz - - 12 ns Output to non-Hi-Z Timeslot 1, bit 7 tnz 15 - - ns Input Clock Frequency Crystals - - 27 MHz CLKIN (Note 10) 1.024 - 13.5 MHz Input Clock (CLKIN) low time 30 - - ns Input Clock (CLKIN) high time 30 - - ns Sample rate Fs 4 - 50 kHz RESET low time (Note 11) 500 - - ns Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%. When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT. See Internal Clock Generation section. 9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec (CLKIN, XTAL1, XTAL2). 10. Sample rate specifications must not be exceeded. 11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage reference to settle. CS4215 DS76F2 5 |
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