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CS4329-KS 데이터시트(PDF) 3 Page - Cirrus Logic |
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CS4329-KS 데이터시트(HTML) 3 Page - Cirrus Logic |
3 / 36 page CS4329 DS153F1 3 ANALOG CHARACTERISTICS (CONTINUED) Notes: 1. Triangular PDF Dithered Data 2. AUTO-MUTE active. See parameter definitions 3. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz, the passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs. 4. Group Delay for Fs=48 kHz 25/48 kHz=520 µs 5. Specified for a fully differential output ±((AOUT+)-(AOUT-)). See Figure 12. SWITCHING CHARACTERISTICS (T A= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = VA = 5.25 to 4.75 Volts; CL =20 pF) Parameter Symbol Min Typ Max Unit Analog Output Differential Full Scale Output Voltage (Note 5) 1.90 2.0 2.10 Vrms Output Common Mode Voltage - 2.2 - V Differential Offset - 3 15 mV AC Load Resistance RL 4- - k Ω Load Capacitance CL - - 100 pf Parameter Symbol Min Typ Max Unit Input Sample Rate Fs 1 - 50 kHz MCLK Pulse Width High MCLK / LRCK = 512 10 - - ns MCLK Pulse Width Low MCLK / LRCK = 512 10 - - ns MCLK Pulse Width High MCLK / LRCK = 384 21 - - ns MCLK Pulse Width Low MCLK / LRCK = 384 21 - - ns MCLK Pulse Width High MCLK / LRCK = 256 31 - - ns MCLK Pulse Width Low MCLK / LRCK = 256 32 - - ns External SCLK Mode SCLK Pulse Width Low tsclkl 20 --ns SCLK Pulse Width High tsclkh 20 --ns SCLK Period tsclkw --ns SCLK rising to LRCK edge delay tslrd 20 --ns SCLK rising to LRCK edge setup time tslrs 20 --ns SDATA valid to SCLK rising setup time tsdlrs 20 --ns SCLK rising to SDATA hold time tsdh 20 --ns Internal SCLK Mode SCLK Period SCLK / LRCK = 64 tsclkw --ns SDATA valid to SCLK rising setup time tsdlrs --ns SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512 tsdh --ns SCLK rising to SDATA hold time MCLK / LRCK = 384 tsdh --ns 1 128 Fs () -------------------- 1 64 Fs () ----------------- 1 512 Fs () -------------------- 10 + 1 512 Fs () -------------------- 15 + 1 384 Fs () -------------------- 15 + |
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