CS4362

8

Notes: 16. See Table 5 on page 26 for suggested MCLK frequencies

17. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

18. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK

.

Parameters

Symbol

Min

Typ

Max

Units

MCLK Frequency

(Note 16)

Single Speed Mode

1.024

-

51.2

MHz

Double Speed Mode

6.400

-

51.2

MHz

Quad Speed Mode

6.400

-

51.2

MHz

MCLK Duty Cycle

40

50

60

%

Input Sample Rate

Single Speed Mode

Double Speed Mode

Quad Speed Mode

Fs

Fs

Fs

4

50

100

-

-

-

50

100

200

kHz

kHz

kHz

LRCK Duty Cycle

45

50

55

%

SCLK Pulse Width Low

20

-

-

ns

SCLK Pulse Width High

20

-

-

ns

SCLK Period

--

ns

(Note 17)

--

ns

SCLK rising to LRCK edge delay

20

-

-

ns

SCLK rising to LRCK edge setup time

20

-

-

ns

SDATA valid to SCLK rising setup time

20

-

-

ns

SCLK rising to SDATA hold time

20

-

-

ns

LRCK1 to LRCK2 frequency ratio

(Note 18)

0.25

1.00

4.00

2

MCLK

------------------

4

MCLK

------------------

sclkh

t

slrs

t

slrd

t

sd lrs

t

sd h

t

sclkl

t

SD ATA

SC LK

LRCK

Figure 1. Serial Mode Input Timing