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CDB4360 데이터시트(PDF) 9 Page - Cirrus Logic |
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CDB4360 데이터시트(HTML) 9 Page - Cirrus Logic |
9 / 36 page CS4360 DS517PP1 9 SWITCHING CHARACTERISTICS (For -KS & -KZ parts T A = -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLS = 1.7 V to 5.5 V; Inputs: Logic 0 = 0 V, Logic 1 = VLS CL = 20 pF) Notes: 15. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled. Parameters Symbol Min Typ Max Units Input Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs 4 50 100 - - - 50 100 200 kHz kHz kHz LRCK Duty Cycle 45 50 55 % MCLK Duty Cycle 405060 % SCLK Frequency - -MCLK/2 Hz SCLK Frequency Note 15 - -MCLK/4 Hz SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDATA hold time tsdh 20 - - ns Figure 1. Serial Mode Input Timing sclkh t slrs t slrd t sdlrs t sdh t sclkl t SDATA SCLK LRCK |
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