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CS4630 데이터시트(PDF) 7 Page - Cirrus Logic |
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CS4630 데이터시트(HTML) 7 Page - Cirrus Logic |
7 / 38 page CS4630 DS445PP1 7 PCI INTERFACE PINS (T A =0° to 70° C; PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V; Timing reference levels = 1.4 V) Notes: 15. For Active/Float measurements, the Hi-Z or “off” state is when the total current delivered is less than or equal to the leakage current. Specification is guaranteed by design, not production tested. 16. RST# is asserted and de-asserted asynchronously with respect to PCICLK. 17. All output drivers are asynchronously floated when RST# is active. 18. REQ# and GNT# are point to point signals. All other PCI signals are considered bused signals. Parameter Symbol Min Max Unit PCICLK cycle time tcyc 30 - ns PCICLK high time thigh 11 - ns PCICLK low time tlow 11 - ns PCICLK to signal valid delay - bused signals (Note 18) tval 211 ns PCICLK to signal valid delay - point to point (Note 18) tval(p+p) 212 ns Float to active delay (Note 15) ton 1- ns Active to Float delay (Note 15) toff -28 ns Input Set up Time to PCICLK - bused signals (Note 18) tsu 7- ns Input Set up Time to PCICLK - point to point (Note 18) tsu(p+p) 10, 12 - ns Input hold time for PCICLK th 0- ns Reset active time after PCICLK stable (Note 16) trst-clk 100 - µs Reset active to output float delay (Notes 15, 16, 17) trst-off -30 ns PCICLK t rst-clk RST# OUTPUTS Hi-Z INPUTS Valid Input t on t off tsu t h OUTPUTS Valid t val trst-off Figure 2. PCI Timing Measurement Conditions |
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