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CS5330A-KS 데이터시트(PDF) 8 Page - Cirrus Logic

부품명 CS5330A-KS
상세설명  8-Pin, Stereo A/D Converter for Digital Audio
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5330A-KS 데이터시트(HTML) 8 Page - Cirrus Logic

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GENERAL DESCRIPTION
The CS5330A and CS5331A are 18-bit, 2-chan-
nel Analog-to-Digital Converters designed for
digital audio applications. Each device uses two
one-bit delta-sigma modulators which simultane-
ously sample the analog input signals at 128
times the output sample rate (Fs). The resulting
serial bit streams are digitally filtered, yielding
pairs of 18-bit values. This technique yields
nearly ideal conversion performance independent
of input frequency and amplitude. The converters
do not require difficult-to-design or expensive
anti-alias filters and do not require external sam-
ple-and-hold amplifiers or a voltage reference.
The CS5330A and CS5331A differ only in the
output serial data format. These formats are dis-
cussed in the following sections and shown in
Figures 2 and 3.
An on-chip voltage reference provides for a sin-
gle-ended input signal range of 4.0 Vpp. Output
data is available in serial form, coded as 2’s
complement 18-bit numbers. Typical power con-
sumption is 150 mW which can be further
reduced to 0.5 mW using the Power-Down
mode.
For more information on delta-sigma modula-
tion, see the references at the end of this data
sheet.
SYSTEM DESIGN
Very few external components are required to
support the ADC. Normal power supply decou-
pling components and a resistor and capacitor on
each input for anti-aliasing are all that’s required,
as shown in Figure 1.
Master Clock
The master clock (MCLK) runs the digital filter
and is used to generate the delta-sigma modula-
tor sampling clock. Table 1 shows some common
master clock frequencies. The output sample rate
is equal to the frequency of the Left / Right
Clock (LRCK). The serial nature of the output
data results in the left and right data words being
read at different times. However, the words
within an LRCK cycle represent simultaneously
sampled analog inputs. The serial clock (SCLK)
shifts the digitized audio data from the internal
data registers via the SDATA pin.
Serial Data Interface
The CS5330A and CS5331A can be operated in
either Master mode, where SCLK and LRCK are
outputs, or SLAVE mode, where SCLK and
LRCK are inputs.
Master Mode
In Master mode, SCLK and LRCK are outputs
which are internally derived from MCLK. The
CS5330A/31A will divide MCLK by 4 to gener-
ate a SCLK which is 64
× Fs and by 256 to
generate LRCK. The CS5330A and CS5331A
can be placed in the Master mode with a
47 kohm pull-down resistor on the SDATA pin
as shown in Figure 1.
Slave Mode
LRCK and SCLK become inputs in SLAVE
mode. LRCK must be externally derived from
MCLK and be equal to Fs. The frequency of
SCLK should be equal to 64
× LRCK, though
other frequencies are possible.
MCLK frequencies of 256
×, 384×, and 512× Fs
are supported. The ratio of the applied MCLK to
LRCK
(kHz)
MCLK (MHz)
256
×
384
×
512
×
32
8.1920
12.2880
16.3840
44.1
11.2896
16.9344
22.5792
48
12.2880
18.4320
24.5760
Table 1. Common Clock Frequencies
CS5330A/CS5331A
8
DS138F2


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