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CS493253-IL 데이터시트(PDF) 7 Page - Cirrus Logic

부품명 CS493253-IL
상세설명  Multi-Standard Audio Decoder Family
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

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CS49300 Family DSP
DS339PP4
7
1.5. Switching Characteristics — RESET
(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Notes: 1. The minimum RESET pulse listed above is valid only when using the recommended pull-up/pull-down
resistors on the RD, WR, PSEL and ABOOT mode pins. For Rev. D and older parts, pull-up/pull-down
resistors may be 4.7 k or 3.3 k. For Rev. E and newer parts, pull-up/pull-down resistors must be 3.3 k.
2. This specification is characterized but not production tested.
1.6. Switching Characteristics — CLKIN
(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
RESET minimum pulse width low (-CL)
(Note 1)
Trstl
100
-
µs
RESET minimum pulse width low (-IL)
(Note 1)
Trstl
530
-
µs
All bidirectional pins high-Z after RESET low
(Note 2)
Trst2z
-50
ns
Configuration bits setup before RESET high
Trstsu
50
-
ns
Configuration bits hold after RESET high
Trsthld
15
-
ns
Parameter
Symbol
Min
Max
Unit
CLKIN period for internal DSP clock mode
Tclki
35
3800
ns
CLKIN high time for internal DSP clock mode
Tclkih
18
ns
CLKIN low time for internal DSP clock mode
Tclkil
18
ns
R ESET
T
rs t2 z
T
rs tl
T
rs ts u
T
rs th ld
RD, W R ,
PSEL, ABO O T
A ll B idirectional
Pins
Figure 1. RESET Timing
CL KIN
Tclkih
Tclkil
Tclki
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable


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