전자부품 데이터시트 검색엔진 |
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M-984-02T 데이터시트(PDF) 3 Page - Clare, Inc. |
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M-984-02T 데이터시트(HTML) 3 Page - Clare, Inc. |
3 / 6 page M-984-02 www.clare.com Rev. 3 3 Pin Functions PIN FUNCTION XIN Crystal Connection — 3.58 MHz crystal across these pins will produce the timebase needed for proper operation of the XOUT M-984-02. An external clock signal may be fed to XIN providing the clock signal has a duty cycle of 50 ±10% and comes within 0.2 volts of the supply rails. XOUT remains unconnected when an external clock is used. X358 A buffered output pin. A 3.58 MHz clock signal is available for use in other circuits as a timebase. Leave open when unused. ENVLP The ENVLP pin is a common detection indicator for the four detect pins. Simply put, the ENVLP is a logical “OR” of the active detect circuits for each of the four windows, though there is a delay provided to permit ENVLP to latch the first active detect pin. ENVLP is not tri-state controlled. V SS The power supply pins, V DD being the most positive. Commonly, VDD is at 3-5 volts, white VSS is at ground. V DD SIGIN Analog signal input. (Internally capacitively coupled.) V REF V REF is a bias voltage generated in the chip for use in external analog circuits, such as active filters and AC-coupled buffers. Leave open when unused. OE The tri-state control pin. OE places the DET pins in the active mode when at logic “1”. When at logic “0,” OE causes the DET outputs to appear as high impedance. Should be tied to logic “1” when the M-984-02 is not used in a time-shared bus application. D1800 D1400 The detect outputs associated with each window. Tri-state control is available through use of the OE pin. D950 Timing is shown in the Timing Diagram on page 4. D400 |
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