전자부품 데이터시트 검색엔진 |
|
ISL12020MIRZ 데이터시트(PDF) 7 Page - Intersil Corporation |
|
ISL12020MIRZ 데이터시트(HTML) 7 Page - Intersil Corporation |
7 / 34 page ISL12020M 7 FN6667.5 December 13, 2011 FoutV Oscillator Stability vs Voltage 2.7V VDD 5.5V -3 +3 ppm 15 Temperature Sensor Accuracy VDD = VBAT = 3.3V ±2 °C 15 IRQ/FOUT (OPEN DRAIN OUTPUT) VOL Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V VDD = 2.7V, IOL = 1mA 0.4 V DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA= -40°C to +85°C,unlessotherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER CONDITIONS MIN (Note 8) TYP (Note 9) MAX (Note 8) UNITS NOTES Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER CONDITIONS MIN (Note 8) TYP (Note 9) MAX (Note 8) UNITS NOTES VDDSR- VDD Negative Slew Rate 10 V/ms 14 VDDSR+ VDD Positive Slew Rate, Minimum .05 V/ms 17 I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 8) TYP (Note 9) MAX (Note 8) UNITS NOTES VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x VDD V15, 16 VOL SDA Output Buffer LOW Voltage, Sinking 3mA VDD = 5V, IOL = 3mA 0 0.02 0.4 V CPIN SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, VDD = 5V, VIN =0V, VOUT = 0V 10 pF 15, 16 fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD. 600 ns |
유사한 부품 번호 - ISL12020MIRZ |
|
유사한 설명 - ISL12020MIRZ |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |