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ISL29044A 데이터시트(PDF) 4 Page - Intersil Corporation

부품명 ISL29044A
상세설명  Low Power Ambient Light and Proximity Sensor with Internal IR-LED and Digital Output
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL29044A 데이터시트(HTML) 4 Page - Intersil Corporation

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ISL29044
4
FN8305.0
October 30, 2012
VIL
SCL and SDA Input Low Voltage
0.55
V
VIH
SCL and SDA Input High Voltage
1.25
V
ISDA
SDA Current Sinking Capability
VOL = 0.4V
3
5
mA
IINT
INT Current Sinking Capability
VOL = 0.4V
3
5
mA
PSRRIRDR
(
ΔIIRDR)/(ΔVIRDR)
PROX_DR = 0; VIRDR = 0.5V to 4.3V
5.8
mA/V
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light source of the same lux
level.
8. Ability to guarantee IIRDR leakage of ~1nA is limited by test hardware.
9. For ALS applications under light-distorting glass, please see the section titled “ALS Range 1 Considerations” on page 9.
Electrical Specifications VDD = 3.0V, TA = +25°C. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 6) TYP
MAX
(Note 6) UNIT
IR-LED Specifications TA = +25°C
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
VF
IR-LED Forward Voltage Drop
IF = 200mA
2.0
V
IF = 100mA
1.8
V
IR
IR-LED Reverse-Bias Current
VR = 5.5V
0.061
5
µA
λP
IR-LED Peak Output Wavelength
IF = 110mA
858
nm
Δλ
IR-LED Spectral Half-Width
IF = 110mA
39
nm
ΦE
IR-LED Radiant Power
IF = 110mA
30
mW
I
IR-LED Radiant Intensity (in 0.01sr) at 0°
IF = 110mA
128
mW/sr
I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C (Note 10).
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 6)
TYP
MAX
(Note 6) UNIT
VI2C
Supply Voltage Range for I2C Interface
1.7
3.63
V
fSCL
SCL Clock Frequency
400
kHz
VIL
SCL and SDA Input Low Voltage
0.55
V
VIH
SCL and SDA Input High Voltage
1.25
V
Vhys
Hysteresis of Schmitt Trigger Input
0.05VDD
V
VOL
Low-level Output Voltage (Open-drain) at 4mA Sink
Current
0.4
V
Ii
Input Leakage for each SDA, SCL Pin
-10
10
µA
tSP
Pulse Width of Spikes that must be Suppressed by
the Input Filter
50
ns
tAA
SCL Falling Edge to SDA Output Data Valid
900
ns
Ci
Capacitance for each SDA and SCL Pin
1pF
tHD:STA
Hold Time (Repeated) START Condition
After this period, the first clock pulse is
generated.
600
ns
tLOW
LOW Period of the SCL Clock
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
HIGH period of the SCL Clock
600
ns


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