전자부품 데이터시트 검색엔진 |
|
CDCV850DGGR 데이터시트(PDF) 1 Page - Texas Instruments |
|
CDCV850DGGR 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 20 page CDCV850 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications D Spread Spectrum Clock Compatible D Operating Frequency: 60 to 140 MHz D Low Jitter (cyc−cyc): ±75 ps D Distributes One Differential Clock Input to Ten Differential Outputs D Two-Line Serial Interface Provides Output Enable and Functional Control D Outputs Are Put Into a High-Impedance State When the Input Differential Clocks Are <20 MHz D 48-Pin TSSOP Package D Consumes <250-μA Quiescent Current D External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks description The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are con- trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA, SCLK), and the analog power input (AVDD). A two-line serial interface can put the individual output clock pairs in a high-impedance state. When the AVDD terminal is tied to GND, the PLL is turned off and bypassed for test purposes. The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ). Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in applications where this programming option is not required (after power up, all output pairs will then be enabled). When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz), the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI. Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up, as well as changes to various 2-line serial registers that affect the PLL. The CDCV850 is characterized in a temperature range from −40°C to 85°C. Copyright © 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ SCLK CLK CLK VDDI AVDD AGND GND Y3 Y3 VDDQ Y4 Y4 GND GND Y5 Y5 VDDQ Y6 Y6 GND GND Y7 Y7 VDDQ SDATA FBIN FBIN VDDQ FBOUT FBOUT GND Y8 Y8 VDDQ Y9 Y9 GND DGG PACKAGE (TOP VIEW) |
유사한 부품 번호 - CDCV850DGGR |
|
유사한 설명 - CDCV850DGGR |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |