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KMPC8315CVRAGDA 데이터시트(PDF) 4 Page - Freescale Semiconductor, Inc |
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KMPC8315CVRAGDA 데이터시트(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 106 page  MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 4 Freescale Semiconductor MPC8315E Features — Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62). • Cyclical Redundancy Check Hardware Accelerator (CRCA) — Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required for IEEE 802 packets, as well as for programmable 32 bit CRC polynomials 2.4 DDR Memory Controller The DDR1/DDR2 memory controller includes the following features: • Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM • Support for up to 266 MHz data rate • Support for two physical banks (chip selects), each bank independently addressable • 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16 data ports (no direct x4 support) • Support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16-bit devices on a 32-bit bus • Support for up to 16 simultaneous open pages • Supports auto refresh • On-the-fly power management using CKE • 1.8-/2.5-V SSTL2 compatible I/O 2.5 PCI Controller The PCI controller includes the following features: • Designed to comply with PCI Local Bus Specification Revision 2.3 • Single 32-bit data PCI interface operates at up to 66 MHz • PCI 3.3-V compatible (not 5-V compatible) • Support for host and agent modes • On-chip arbitration, supporting three external masters on PCI • Selectable hardware-enforced coherency 2.6 TDM Interface The TDM interface includes the following features: • Independent receive and transmit with dedicated data, clock and frame sync line • Separate or shared RCK and TCK whose source can be either internal or external • Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses • Up to 128 time slots, where each slot can be programmed to be active or inactive • 8- or 16-bit word widths • The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock |
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