SL28EB742

10

Preliminary Rev. 0.1

2.3. Powerdown (PD) Deassertion

The powerup latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the

power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a

three-state condition resulting from powerdown are driven high in less than 300 µs of PD deassertion to a voltage

greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a

few clock cycles of each clock. Figure 2 is an example showing the relationship of clocks coming up.

Figure 1. Powerdown Assertion Timing Waveform

Figure 2. Powerdown Deassertion Timing Waveform

PD

USB, 48MHz

DOT96T

DOT96C

SRCT 100MHz

SRCC 100MHz

CPUT, 133MHz

PCI, 33 MHz

REF

CPUC, 133MHz

DOT96C

PD

CPUC, 133MHz

CPUT, 133MHz

SRCC 100MHz

USB, 48MHz

DOT96T

SRCT 100MHz

Tstable

<1.8 ms

PCI, 33MHz

REF

Tdrive_PWRDN

<300

s, >200 mV