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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TSB81BA3EIPFP 데이터시트(PDF) 8 Page - Texas Instruments |
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TSB81BA3EIPFP 데이터시트(HTML) 8 Page - Texas Instruments |
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8 / 58 page  TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL PFP ZAJ DESCRIPTION PACKAGE PACKAGE NAME TYPE NO. NO. I/O 21, 40, 43, Analog circuit ground terminals. These terminals must be tied together to AGND(1) Supply See DGND – 50, 61, 62 the low-impedance circuit board ground plane. Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 mF and 0.001 mF. Lower frequency 10-mF filtering capacitors are also M4, F10, 24, 39, 44, recommended. These supply terminals are separated from the AVDD-3.3 Supply H10, J10, – 51, 57, 63 PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and DVDD-3.3 terminals E10 internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board. Beta-mode input. This terminal determines the PHY-link interface connection protocol. When logic-high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-link interface. When logic-low (deasserted), the PHY-link interface complies with the legacy 1394a-2000 BMODE CMOS 74 B6 I standard. When using an LLC such as the 1394b-2002 TSB82AA2, this terminal must be pulled high. When using an LLC such as the 1394a-2000 TSB12LV26, this terminal must be tied low. NOTE: The PHY-link interface cannot be changed between the different protocols during operation. Cable not active output. This terminal is asserted high when there are no CNA CMOS 79 A2 O ports receiving incoming bias voltage. When any port receives bias, this terminal goes low. Cable-power status input. This terminal is normally connected to cable power through a 400-k Ω resistor. This circuit drives an internal comparator CPS CMOS 34 N9 I that detects the presence of cable power. This transition from cable power sensed to cable power not sensed can be used to generate an interrupt to the LLC. CTL0 9 F1 Control I/Os. These bidirectional signals control communication between the CMOS I/O CTL1 10 G1 TSB81BA3E and the LLC. Bus holders are built into these terminals. 11, 12, 13, H1, H2, J2, Data I/Os. These are bidirectional data signals between the TSB82BA3 and D0-D7 CMOS 15, 16, 17, J1, K2, K1, I/O the LLC. Bus holders are built into these terminals. 19, 20 L1, M1 E5, F4, F5, F6, F7, F9, G4, G5, G6, G7, G8, G9, 4, 14, 38, 64, Digital circuit ground terminals. These terminals must be tied together to the DGND(1) Supply G10, H4, H5, – 72, 76 low-impedance circuit board ground plane. H6, H7, H8, J4, J5, J6, J7, J8, K7, L7 Data-strobe-only mode for port 0. 1394a-only port 0 enable programming terminal. On hardware reset, this terminal allows the user to select whether port 0 acts like a 1394b bilingual port (terminal at logic 0) or as a DS0 CMOS 33 N8 I 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-k Ω or less resistor (to enable 1394b bilingual mode) or high through a 1-k Ω or less resistor (to enable 1394a-2000-only mode). A bus holder is built into this terminal. Data-strobe-only mode for port 1. 1394a-only port 1 enable programming terminal. On hardware reset, this terminal allows the user to select whether port 1 acts like a 1394b bilingual port (terminal at logic 0) or as a DS1 CMOS 32 M7 I 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-k Ω or less resistor (to enable 1394b bilingual mode) or high through a 1-k Ω or less resistor (to enable 1394a-2000-only mode). A bus holder is built into this terminal. (1) All AGND and DGND terminals are internally tied together in the ZAJ package. 8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TSB81BA3E |
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