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TSL1401CS 데이터시트(PDF) 3 Page - ams AG |
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TSL1401CS 데이터시트(HTML) 3 Page - ams AG |
3 / 19 page TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 2 r r Copyright E 2007, TAOS Inc. The LUMENOLOGY r Company www.taosinc.com Terminal Functions TERMINAL DESCRIPTION NAME NO. DESCRIPTION AO 6 Analog output CLK 3 Clock. The clock controls charge transfer, pixel output, and reset. GND 4, 5 Ground (substrate). All voltages are referenced to the substrate. HOLD 2 Hold signal. HOLD freezes the result of a 128 pixel scan. SI 1 Serial input. SI defines the start of the data-out sequence. SO 7 Serial output. SO provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. VDD 8 Supply voltage. Supply voltage for both analog and digital circuits. Detailed Description The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. The signal called Hold is normally connected to SI. Then, the rising edge of SI causes a HOLD condition. This causes all 128 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the 129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and return the internal logic to a known state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum delay of tqt (pixel charge transfer time) after the 129th clock pulse. AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout is the analog output voltage for white condition Vdrk is the analog output voltage for dark condition Re is the device responsivity for a given wavelength of light given in V/(μJ/cm2) Ee is the incident irradiance in μW/cm2 tint is integration time in seconds A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device. The TSL1401CS−LF is intended for use in a wide variety of applications, including: image scanning, mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding. |
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