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ADC08DL500 데이터시트(PDF) 11 Page - Texas Instruments

부품명 ADC08DL500
상세설명  ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter
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I / O
GND
V
A
TO INTERNAL
CIRCUITRY
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Converter Electrical Characteristics Static Converter Characteristics
The following specifications apply after calibration for VA = VDR = 1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 840
mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 500 MHz at 0.5 VP-P with 50% duty cycle; VBG =
Floating; Extended Control Mode default values; DDR 0° Mode; REXT = 4700 Ω ±0.1%; 1:2 Output Demultiplex; Duty Cycle
Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.
(1) (2).
Units
Symbol
Parameter
Conditions
Typ(3)
Lim
(Limits)
Resolution with No Missing Codes
8
Bits
INL
Integral Non-Linearity
DC Coupled, 1 MHz Sine Wave
±0.3
±0.9
LSB (max)
(Best fit)
Overanged, SDR, Non-ECM, FSR
= High
DNL
Differential Non-Linearity
DC Coupled, 1 MHz Sine Wave
±0.15
±0.75
LSB (max)
Overanged, SDR, Non-ECM, FSR
= High
VOFF
Offset Error
SDR, Non-ECM Mode
−0.45
LSB
VOFF_ADJ
Input Offset Adjustment Range (4)
Extended Control Mode
±45
mV
PFSE
Positive Full-Scale Error
(5)
±25
mV (max)
NFSE
Negative Full-Scale Error
(5)
±25
mV (max)
Out of Range Output Code
(VIN+) − (VIN−) > + Full Scale
255
(VIN+) − (VIN−) < − Full Scale
0
(1)
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
(2)
To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded.
(3)
Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average
Outgoing Quality Level).
(4)
Only the end points of the range, not the full sweep, are tested in production test.
(5)
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for
this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. For relationship between Gain Error and Full-
Scale Error, see Specification Definitions for Gain Error.
Copyright © 2011, Texas Instruments Incorporated
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