9

Digital Interface Configuration

Configuration Registers

The Digital Interface IC contains four 6-bit configuration

registers that control its behavior. The two LSBs of any

byte clocked into the serial configuration port (CDAT,

CCLK, CLAT) are used as address bits to determine which

register the data will be loaded into. Registers 0 and 1

(with address bits 00 and 01) specify the conversion and

offset calibration modes of channels 1 and 2, register 2

(address bits 10) specifies the behavior of the adjustable

threshold circuit, and register 3 (address bits 11) specifies

which pre-trigger mode to use for channel 1. These

registers are illustrated in Table 1 below, with default

values indicated in bold italic type. Note that there are

several reserved bits, which should always be set low and

that the configuration registers should not be changed

during a conversion cycle.

Table 1. Register Configuration.

Table 2. Conversion Mode Configuration.

Notes: Bold italic type indicates Default values.

Conversion

Mode

Configuration Data Bits

Bit 7

Bit 6

Bit 5

Bit 4

1

Low

High

Low

High

2

Low

Low

High

High

3

High

High

High

Low

4

High

High

Low

Low

5

High

Low

High

Low

Conversion Mode

The conversion mode determines the speed/resolution

trade-off for the Isolated A/D converter. The four MSBs

of registers 0 and 1 determine the conversion mode for

the appropriate channel. The bit settings for choosing a

particular conversion mode are shown in Table 2 below.

Combinations of data bits not specified in Table 2 below

are not recommended.

Notes: Bold italic type indicates Default values. Reserved bits should be set low.

Configuration Data Bits

Address Bit

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

Channel 1 Conversion Mode

Channel 1

Offset Cal

Reserved

High

High

Low

Low

Low

Low

Low

Low

1

Channel 2 Conversion Mode

Channel 2

Offset Cal

Reserved

High

High

Low

Low

Low

Low

Low

High

2

Threshold Detection

Time

Threshold Level

High

Low

Low

Low

Low

Low

High

Low

3

Pre-Trigger Mode

Reserved

Low

Low

Low

Low

Low

Low

High

High