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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TDA8020HLC2 데이터시트(PDF) 9 Page - NXP Semiconductors |
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TDA8020HLC2 데이터시트(HTML) 9 Page - NXP Semiconductors |
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9 / 28 page  2003 Nov 06 9 Philips Semiconductors Product specification Dual IC card interface TDA8020HL called the master. The devices that are controlled by the master are called slaves. Each byte is followed by one HIGH-level acknowledge bit asserted by the transmitter. The master generates an extra acknowledge related clock pulse. The slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. The master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull-down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master generation of the STOP condition. See Chapter “Characteristics” for timing information. DEVICE ADDRESSING Each device has 2 different addresses, one for each card. An application can use up to four devices in parallel by the use of address selection pins SAD0 and SAD1. Pins SAD0 and SAD1 are externally hardwired to VDD or GND; SAD0 specifies address bit A0, SAD1 specifies address bit A1; Address bit R/W specifies either read or write operation: logic 1 = Read, logic 0 = Write (see Tables 1 and 2). Table 1 Proposed device address bit allocations Table 2 Proposed I2C-bus addresses for 4 devices in parallel Device Address bits 76543210 TDA8020HL 0 1 0 0 0/1 A1 A0 R/W PIN SAD1 PIN SAD0 CARD 1 CARD 2 LOW LOW 40H 48H LOW HIGH 42H 4AH HIGH LOW 44H 4CH HIGH HIGH 46H 4EH |
유사한 부품 번호 - TDA8020HLC2 |
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