74HC_HCT00_Q100

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Product data sheet

Rev. 1 — 12 July 2012

2 of 15

NXP Semiconductors

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

3.

Ordering information

4.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC00D-Q100

40 C to +125 C

SO14

plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT00D-Q100

74HC00PW-Q100

40 C to +125 C

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT00PW-Q100

74HC00BQ-Q100

40 C to +125 C

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5

 3  0.85 mm

SOT762-1

74HCT00BQ-Q100

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

mna212

1A

1Y

1B

1

2

3

2A

2Y

2B

4

5

6

3A

3Y

3B

9

10

8

4A

4Y

4B

12

13

11

mna246

3

1

2

&

6

4

5

&

8

9

10

&

11

12

13

&

mna211

A

B

Y