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74HC00-Q100 데이터시트(PDF) 3 Page - NXP Semiconductors |
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74HC00-Q100 데이터시트(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 74HC_HCT00_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 12 July 2012 3 of 15 NXP Semiconductors 74HC00-Q100; 74HCT00-Q100 Quad 2-input NAND gate 5. Pinning information 5.1 Pinning 5.2 Pin description 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 74HC00-Q100 74HCT00-Q100 1A VCC 1B 4B 1Y 4A 2A 4Y 2B 3B 2Y 3A GND 3Y aaa-003147 1 2 3 4 5 6 7 8 10 9 12 11 14 13 aaa-003148 74HC00-Q100 74HCT00-Q100 GND(1) Transparent top view 2Y 3A 2B 3B 2A 4Y 1Y 4A 1B 4B 6 9 5 10 4 11 3 12 2 13 terminal 1 index area Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage Table 3. Function table[1] Input Output nA nB nY LX H XL H HHL |
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