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FDD3682_F085 데이터시트(PDF) 8 Page - Fairchild Semiconductor |
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FDD3682_F085 데이터시트(HTML) 8 Page - Fairchild Semiconductor |
8 / 11 page PSPICE Electrical Model .SUBCKT FDD3682 2 1 3 ; rev Jun 2002 Ca 12 8 4e-10 Cb 15 14 6e-10 Cin 6 8 1.22e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 112 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 4.88e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.24e-9 RLgate 1 9 48.8 RLdrain 2 5 10 RLsource 3 7 22.4 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 10.5e-3 Rgate 9 20 1.8 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 11.9e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),2.5))} .MODEL DbodyMOD D (IS=2.4E-12 RS=4.4e-3 TRS1=2.0e-3 TRS2=4.5e-7 + CJO=9e-10 M=0.58 TT=2.9e-8 XTI=4.0) .MODEL DbreakMOD D (RS=0.6 TRS1=1.4e-3 TRS2=-5.0e-5) .MODEL DplcapMOD D (CJO=2.75e-10 IS=1.0e-30 N=10 M=0.56) .MODEL MstroMOD NMOS (VTO=4.16 KP=32 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.48 KP=2.7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.8) .MODEL MweakMOD NMOS (VTO=2.96 KP=0.068 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=18 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1.1e-8) .MODEL RdrainMOD RES (TC1=1.5e-2 TC2=4e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.9e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-3.5e-3 TC2=1.3e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-2.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-5.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 18 22 + - 6 8 + - 5 51 19 8 + - 17 18 6 8 + - 5 8 + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 19 22 12 13 15 S1A S1B S2A S2B CA CB EGS EDS 14 8 13 8 14 13 MWEAK EBREAK DBODY RSOURCE SOURCE 11 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 16 21 8 MMED MSTRO DRAIN 2 LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 10 5 51 50 RSLC2 1 GATE RGATE EVTEMP 9 ESG LGATE RLGATE 20 + - + - + - 6 ©2010 Fairchild Semiconductor Corporation FDD3682_F085 Rev. A |
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