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AD532 데이터시트(PDF) 11 Page - Analog Devices

부품명 AD532
상세설명  Internally Trimmed Integrated Circuit Multiplier
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AD532 데이터시트(HTML) 11 Page - Analog Devices

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AD532
Rev. D | Page 10 of 16
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in
Figure 1and the complete schematic in Figure 14. In the
multiplying and squaring modes, Z is connected to the output
to close the feedback around the output op amp. In the divide
mode, it is used as an input terminal.
The X and Y inputs are fed to high impedance differential
amplifiers featuring low distortion and good common-mode
rejection. The amplifier voltage offsets are actively laser trimmed to
zero during production. The product of the two inputs is resolved
in the multiplier cell using Gilbert’s linearized transconductance
technique. The cell is laser trimmed to obtain VOUT = (X1
X2)(Y1 − Y2)/10 volts. The built-in op amp is used to obtain low
output impedance and make possible self-contained operation.
The residual output voltage offset can be zeroed at VOS in critical
applications. Otherwise, the VOS pin should be grounded.
X2
X1
Y1
COM
R2
R34
R9
R1
Q1
Q2
Q3
Q4
Q5
Q6
R3
R6
R8
R16
Q7 Q8
Q14 Q15
Q9
Q10
R13
Y2
R18
R4
R5
R10
R32
Q28
Q11
Q12
R11
R19
R14
R12
R15
Q13
Q16 Q17
R23
R20
R22
R21
C1
Q21
R27
Q25
Z
R33
VOS
OUTPUT
R30
R28
R29
R31
Q26
Q27
Q22
Q23
Q24
R26
R25
R24
Q20
Q19
Q18
+VS
–VS CAN
Figure 14. Schematic Diagram


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