전자부품 데이터시트 검색엔진 |
|
AD807 데이터시트(PDF) 7 Page - Analog Devices |
|
AD807 데이터시트(HTML) 7 Page - Analog Devices |
7 / 12 page REV. B AD807 –7– RMS JITTER – Degrees 30 0 1.4 2.3 1.5 1.6 1.7 1.8 2.2 20 5 15 25 10 1.9 2.0 2.1 TEST CONDITIONS WORST-CASE: –40 C, 4.5V TPC 7. Output Jitter Histogram FREQUENCY – Hz 1E+3 100E–3 10E+0 10E+6 10E+0 100E+0 1E+3 10E+3 100E+3 100E+0 1E+0 1E+6 AD807 SONET MASK TPC 8. Jitter Tolerance NOISE – V p-p @ 311MHz 3.0 0 0 0.6 0.1 0.2 0.3 0.4 0.5 2.0 1.0 1.0 0.7 0.8 0.9 PSR – NO FILTER CMR PSR – WITH FILTER TPC 9. Output Jitter vs. Supply Noise and Output Jitter vs. Common Mode Noise THEORY OF OPERATION Quantizer The quantizer (comparator) has three gain stages, providing a net gain of 350. The quantizer takes full advantage of the Extra Fast Complementary Bipolar (XFCB) process. The input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with common- mode voltage as high as the positive supply. The input offset voltage is factory trimmed and guaranteed to be less than 500 µV. XFCB’s dielectric isolation allows the different blocks within this mixed-signal IC to be isolated from each other, hence the 2 mV Sensitivity is achieved. Traditionally, high speed compara- tors are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD807 quantizer toggles at ±650 µV (1.3 mV sensitivity) at the input without making bit errors. When the input signal is lowered below ± 650 µV, circuit performance is dominated by input noise, and not crosstalk. 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F FERRITE BEAD OPTIONAL FILTER 0.1 F 50 309 50 50 3.65k +5V 10 F CHOKE “BIAS TEE” 311MHz NOISE INPUT 0.1 F 0.1 F 500 500 13 12 14 11 6 3 PIN NIN AVCC2 AVCC1 VCC1 VCC2 AD807 0.1 F QUANTIZER INPUT Figure 6. Power Supply Noise Sensitivity Test Circuit 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 50 309 50 50 3.65k +5V 10 F CHOKE “BIAS TEE” 311MHz NOISE INPUT 0.1 F 0.1 F 500 500 13 12 14 11 6 3 PIN NIN AVCC2 AVCC1 VCC1 VCC2 AD807 0.1 F QUANTIZER INPUT Figure 7. Common-Mode Rejection Test Circuit Signal Detect The input to the signal detect circuit is taken from the first stage of the quantizer. The input signal is first processed through a gain stage. The output from the gain stage is fed to both a positive and a negative peak detector. The threshold value is subtracted from the positive peak signal and added to the negative peak signal. The positive and negative peak signals are then compared. If the positive peak, POS, is more positive than the negative peak, NEG, the signal amplitude is greater than the threshold, and the output, SDOUT, will indicate the presence of signal by remain- ing low. When POS becomes more negative than NEG, the signal amplitude has fallen below the threshold, and SDOUT will indicate a loss of signal (LOS) by going high. The circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. This means that the input data amplitude needs to reach twice the set LOS threshold before SDOUT will signal that the data is again valid. This corresponds to a 3 dB optical hysteresis. |
유사한 부품 번호 - AD807_15 |
|
유사한 설명 - AD807_15 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |