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L64250JC15 데이터시트(PDF) 10 Page - InnovASIC, Inc |
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L64250JC15 데이터시트(HTML) 10 Page - InnovASIC, Inc |
10 / 21 page IA64250 Data Sheet Histogram/Hough Transform Processor As of Production Ver. 01 Copyright © 2000 ENG211001219-01 www.innovasic.com innovASIC Customer Support: The End of Obsolescence ™ Page 10 of 21 1-888-824-4184 LUT RAM Hough Transform Mode (45 < φ ≤ 90): Address Memory Contents 0 0*cot φ 1 1*cot φ . . . . . . . . 511 511*cot φ LUT RAM Find Pixel Mode: Memory Contents Address 0-5 6-7 8 0 Flag for Grey Value 0 t0 1 Flag for Grey Value 1 t1 . . . . . . . . Tag Bit 511 Flag for Grey Value 511 t511 Not Used COMPUTATION MODE: Histogram Computation: During histogram computation, the ACC RAM and LUT RAM form the active elements of the data path. The ACC RAM is addressed by the controller block. The ACC RAM address is the DI input signal. The data addressed by the DI signal is incremented if the DV input signal is high, otherwise the data is left unchanged. The LUT is not used in the computation of the histogram and can concurrently modify the image by a user-defined transfer function. The DI signal addresses the LUT and the LUT data appears on the VDO output pins two clock cycles later. Histogram equalization can be performed in real time. The histogram is stored in the ACC RAM. The equalization transfer function must be computed and transferred into the LUT RAM. Then during the next frame as a new histogram is being computed, data will also be equalized in real time and passed to the VDO output pins. |
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