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AD5255 데이터시트(PDF) 10 Page - Analog Devices

부품명 AD5255
상세설명  3-Channel Digital Potentiometer with Nonvolatile Memory
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AD5255 데이터시트(HTML) 10 Page - Analog Devices

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AD5255
Rev. A | Page 10 of 20
INTERFACE DESCRIPTIONS
I2C INTERFACE
All control and access to both EEPROM memory and the
RDAC registers are conducted via a standard 2-wire I2C interface.
Figure 2 shows the timing characteristics of the I2C bus.
Figure 16 and Figure 17 illustrate standard transmit and receive
bus signals in the I2C interface.
These figures use the following legend:
From master to slave
From slave to master
S = Start condition
P = Stop condition
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
R/W = Read enable at high and write enable at low
SLAVE ADDRESS
S
0 = WRITE
A
DATA
A
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)
DATA
A/A
P
R/W
Figure 16. I2C—Master Transmitting Data to Slave
SLAVE ADDRESS
S
1 = WRITE
A
DATA
A
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE
DATA
A
P
R/W
Figure 17. I2C—Master Reading Data from Slave
SLAVE ADDRESS
S
READ OR WRITE
A
DATA
(N BYTES + ACKNOWLEDGE)
A/A
P
R/W
SLAVE ADDRESS
S
READ OR WRITE
REPEATED START
A
DATA
(N BYTES + ACKNOWLEDGE)
A/A
R/W
DIRECTION OF TRANSFER MAY
CHANGE AT THIS POINT
Figure 18. Combined Transmit/Read


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