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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD5382 데이터시트(PDF) 11 Page - Analog Devices |
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AD5382 데이터시트(HTML) 11 Page - Analog Devices |
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11 / 40 page  Data Sheet AD5382 Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) I2C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1, 2 Limit at TMIN, TMAX Unit Description fSCL 400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min tHIGH, SCL high time t3 1.3 µs min tLOW, SCL low time t4 0.6 µs min tHD,STA, start/repeated start condition hold time t5 100 ns min tSU,DAT, data setup time t63 0.9 µs max tHD,DAT, data hold time 0 µs min tHD,DAT, data hold time t7 0.6 µs min tSU,STA, setup time for repeated start t8 0.6 µs min tSU,STO, stop condition setup time t9 1.3 µs min tBUF, bus free time between a stop and a start condition t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible) t11 300 ns max tF, fall time of SDA when transmitting 0 ns min tF, fall time of SDA when receiving (CMOS-compatible) 300 ns max tF, fall time of SCL and SDA when receiving 20 + 0.1Cb4 ns min tF, fall time of SCL and SDA when transmitting Cb 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. 2 See Figure 6. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD. t22 t13 t23 t21 t2 t3 t20 t8 t9 t7 t4 t1 SCLK SYNC SDO DIN LDAC 48 24 DB23 DB0 DB0 DB23 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 UNDEFINED INPUT WORD FOR DAC N Rev. D | Page 11 of 40 |
유사한 부품 번호 - AD5382_15 |
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유사한 설명 - AD5382_15 |
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