전자부품 데이터시트 검색엔진 |
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8XC51 데이터시트(PDF) 6 Page - Intel Corporation |
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8XC51 데이터시트(HTML) 6 Page - Intel Corporation |
6 / 22 page 8XC51GB 272337 – 4 C1 C2 e 30 pF g10 pF for Crystals For Ceramic Resonators contact resonator manufacturer Figure 4 Oscillator Connections 272337 – 5 Figure 5 External Clock Drive Configuration IDLE MODE The user’s software can invoke the Idle Mode When the microcontroller is in this mode power consump- tion is reduced The Special Function Registers and the onboard RAM retain their values during idle pe- ripherals continue to operate but the processor stops executing instructions Idle Mode will be exited if the chip is reset or if an enabled interrupt occurs The PCA timercounter can optionally be left run- ning or paused during Idle Mode The Watchdog Timer continues to count in Idle Mode and must be serviced to prevent a device RESET while in Idle POWER DOWN MODE To save even more power a Power Down mode can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed The on-chip RAM and Special Function Registers retain their val- ues until the Power Down mode is terminated On the 8XC51GB either a hardware reset or an ex- ternal interrupt can cause an exit from Power Down Reset redefines all the SFRs but does not change the on-chip RAM An external interrupt does not re- define the SFR’s or change the on-chip RAM An external interrupt will modify the interrupt associated SFR’s in the same way an interrupt will in all other modes The interrupt must be enabled and config- ured as level sensitive To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal oper- ating level The reset or external interrupt must be held active long enough for the oscillator to restart and stabilize The Oscillator Fail Detect must be dis- abled prior to entering Power Down DESIGN CONSIDERATIONS When the idle mode is terminated by a hardware reset the device normally resumes program exe- cution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to inter- nal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write when Idle is terminated by re- set the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory As RESET rises the 8XC51GB will remain in re- set for up to 5 machine cycles (60 oscillator peri- ods) after RESET reaches VIH1 Table 1 Status of the External Pins during Idle and Power Down Mode Program ALE PSEN PORT0 PORT1 PORT2 PORT3 Memory Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data NOTE For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No 270648) ‘‘Designing with the 80C51BH’’ 6 |
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