전자부품 데이터시트 검색엔진 |
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AD7273 데이터시트(PDF) 9 Page - Analog Devices |
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AD7273 데이터시트(HTML) 9 Page - Analog Devices |
9 / 29 page AD7273/AD7274 Rev. 0 | Page 8 of 28 TIMING EXAMPLES For the AD7274, if CS is brought high during the 14 th SCLK rising edge after the two leading zeros and 12 bits of the conversion are provided, the part can achieve the fastest throughput rate, 3 MSPS. If CS is brought high during the 16 th SCLK rising edge after the two leading zeros, 12 bits of the conversion, and two trailing zeros are provided, a throughput rate of 2.97 MSPS is achievable. This is illustrated in the following two timing examples. Timing Example 1 In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and the throughput is 3 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ. Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET, where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET, satisfying the minimum requirement of 4 ns. Timing Example 2 The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz, and the throughput is 2.97 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum requirement of 4 ns for tQUIET. 12 3 4 5 13 14 15 16 SCLK SDATA THREE-STATE THREE- STATE TWO LEADING ZEROS TWO TRAILING ZEROS B CS t3 tCONVERT t2 ZERO Z DB11 DB10 DB9 DB1 DB0 ZERO ZERO t6 t5 t8 t1 tQUIET 1/THROUGHPUT t4 t7 Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle 12 3 4 5 13 14 SCLK SDATA THREE-STATE THREE- STATE TWO LEADING ZEROS B CS t3 tCONVERT t2 ZERO Z DB11 DB10 DB9 DB1 DB0 t6 t9 t1 tQUIET 1/THROUGHPUT t4 t7 t5 Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle 12 3 4 5 13 12 14 15 16 SCLK B CS tCONVERT t2 t8 t1 tQUIET 1/THROUGHPUT 12.5(1/fSCLK) tACQUISITION Figure 7. Serial Interface Timing 16 SCLK Cycle |
유사한 부품 번호 - AD7273_15 |
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유사한 설명 - AD7273_15 |
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