AD7304/AD7305

Rev. C | Page 8 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

16

15

14

13

12

GND

6

SDI/SHDN

11

LDAC

7

CLK

10

CLR

8

CS

9

AD7304

TOP VIEW

(Not to Scale)

Figure 8. AD7304 Pin Configuration

Table 7. AD7304 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Output is open circuit when SHDN is enabled.

2

Output is open circuit when SHDN is enabled.

3

Negative Power Supply Input. Specified range of operation is 0 V to

−5.5 V.

4

5

6

GND

Common Analog and Digital Ground.

7

LDAC

Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the

corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See

Table 4 for operation.

8

CLR

Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is

not effected.

9

CS

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to

the decoded input register when CS returns high. Does not effect LDAC operation.

10

CLK

Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS.

11

SDI/SHDN

Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input,

active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as

12

13

14

Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V.

15

Output is open circuit when SHDN is enabled.

16

Output is open circuit when SHDN is enabled.