4

Slew Rate (See Figures 2, 4)

SR

No Load

25

-

220

-

V/

µs

25

-

160

-

V/

µs

No Load

25

370

440

-

V/

µs

25

300

330

-

V/

µs

Full Power Bandwidth

(FPBW = SR/

FPBW

No Load

25

-

10

-

MHz

25

-

7.2

-

MHz

No Load

25

29

35

-

MHz

25

24

26

-

MHz

Input Noise Voltage

f = 1kHz

25

-

12

-

nV/

√Hz

Differential Gain

DG

See Figure 8

25

-

0.2

-

%

Differential Phase

DP

See Figure 8

25

-

0.2

-

Degrees

Output Current

Into +4V or -4V

25

60

75

-

mA

Output Voltage Swing

25

3.9

4.1

-

V

25

-3.9

-4.1

-

V

Input Capacitance

f = 1MHz

25

-

2.2

-

pF

Input Resistance

25

-

1

-

M

Ω

Output Resistance

25

-

4

-

Ω

Electrical Specifications

PARAMETER

SYMBOL

TEST CONDITIONS

TEMP.

MIN

TYP

MAX

UNITS

Test Circuits and Waveforms

FIGURE 1. OPEN LOOP GAIN vs FREQUENCY TEST CIRCUIT

13

1

16

12

5

4

CA3450

+

-

OFFSET

NULL

14

3

GEN

50

Ω

50

Ω

8

7

11

9

50

Ω

0.001

µF

1M

20pF

6

0.1

µF

10

Ω (NOTE 2)

-6V

4.7

µF (TANT.)

10

Ω

820pF SILVER MICA

OR EQUIVALENT

MULTILAYER

CERAMIC CHIP

0.1

µF

0.1

µF

10

Ω (NOTE 2)

+6V

4.7

µF (TANT.)

+

-

+

-

SCOPE INPUT

NOTE:

2. A 10

means of decoupling the IC directly at its terminal without introducing additional supply resonance due to parallel connected capacitors. Second,

it also provides protection for the device in event of a sustained short circuit applied directly to the output terminals.

All 0.1

µF and 0.001µF supply decoupling capacitors

are multilayer ceramic chip types.

51K

CA3450