AD7796/AD7797

Rev. A | Page 11 of 24

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip

registers, which are described on the following pages. In the

following descriptions, set implies a Logic 1 State and cleared

implies a Logic 0 State, unless otherwise stated.

COMMUNICATION REGISTER

RS2, RS1, RS0 = 0, 0, 0

The communication register is an 8-bit write-only register. All

communication to the part must start with a write operation to

this register. The data written to the communication register

determines whether the next operation is a read or write opera-

tion, and selects the register where this operation takes place.

Once the subsequent read or write operation to the selected

register is complete, the interface returns to where it expects a

write operation to the communication register (this is the

default state of the interface). On power-up or after a reset, the

ADC is in this default state waiting for a write operation to the

communication register. In situations where the interface

sequence is lost, a write operation of at least 32 serial clock

cycles with DIN high returns the ADC to this default state by

resetting the entire part. Table 9 outlines the bit designations for

the communication register. CR0 through CR7 indicate the bit

location, with CR denoting that the bits are in the communication

register. CR7 denotes the first bit of the data stream. The number

in brackets indicates the power-on/reset default status of that bit.

MSB

LSB

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

WEN(0)

R/W(0)

RS2(0)

RS1(0)

RS0(0)

CREAD(0)

0(0)

0(0)

Table 9. Communication Register Bit Designations

Bit Location

Bit Name

Description

CR7

WEN

Write Enable Bit. A 0 must be written to this bit first to ensure that a write to the communication register

occurs. If a 1 is the first bit written, the part does not clock onto subsequent bits in the register; it stays at this

bit location until a 0 is written. Once a 0 is written to the WEN bit, the next seven bits are loaded to the

communication register.

CR6

R/W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

CR5 to CR3

RS2 to RS0

Register Address Bits. These address bits determine which ADC registers are being selected during this serial

interface communication. See Table 10.

CR2

CREAD

Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured to continuously read the data register. For example, the contents of the data register are

automatically placed on the DOUT pin when the SCLK pulses are applied and after the RDY pin goes low. This

indicates that a conversion is complete. The communication register does not have to be written to for data reads.

To enable continuous read mode, the instruction 01011100 must be written to the communication register.

To exit the continuous read mode, the instruction 01011000 must be written to the communication register

while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so it can

receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen

on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is written to the device.

CR1 to CR0

0

These bits must be programmed to Logic 0 for correct operation.

Table 10. Register Selection

RS2

RS1

RS0

Register

Register Size

0

0

0

Communication Register During a Write Operation

8 bits

0

0

0

Status Register During a Read Operation

8 bits

0

0

1

Mode Register

16 bits

0

1

0

Configuration Register

16 bits

0

1

1

Data Register

16 bits (AD7796), 24 bits (AD7797)

1

0

0

ID Register

8 bits

1

0

1

Reserved

8 bits

1

1

0

Offset Register

16 bits (AD7796), 24 bits (AD7797)

1

1

1

Full-Scale Register

16 bits (AD7796), 24 bits (AD7797)