7-1285

CD40100BMS

FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY

Timing Diagram

FIGURE 9. TIMING DIAGRAM DEFINING SETUP, HOLD, AND PROPAGATION DELAY TIMES

Chip Dimensions and Pad Layout

8

6

4

2

CLOCK INPUT FREQUENCY (fCL) (KHz)

1

6

4

2

SUPPLY VOLTAGE (VDD) = 15V

10V

10V

5V

8

6

4

2

8

6

4

2

8

6

4

2

8

8

6

4

2

10

8

6

4

28

6

4

28

6

4

2

CL = 50pF

CL =15pF

CLOCK

INPUT

OUTPUT

tWH

tWL

tS

tH

tPHL

tPHL

Dimensions in parenthesis are in millimeters and are derived from

the basic inch dimensions as indicated. Grid graduations are in mils

METALLIZATION:

Thickness: 11k

Å

PASSIVATION:

10.4kÅ - 15.6k

BOND PADS:

0.004 inches X 0.004 inches MIN

DIE THICKNESS:

0.0198 inches - 0.0218 inches