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CD40105BMS 데이터시트(PDF) 10 Page - Intersil Corporation

부품명 CD40105BMS
상세설명  CMOS FIFO Register
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제조업체  INTERSIL [Intersil Corporation]
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CD40105BMS 데이터시트(HTML) 10 Page - Intersil Corporation

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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
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CD40105BMS
Chip Dimensions and Pad Layout
FIGURE 11. EXPANSION, 8-BITS-WIDE-BY-16 N-BITS LONG USING CD40105BMS
SI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MR
SO
DOR
SI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MR
SO
DOR
SI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MR
SO
DOR
SI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MR
SO
DOR
SHIFT
IN
DATA OUT
READY
8 BIT
DATA
8 BIT
DATA
SHIFT
OUT
DATA IN
READY
*MASTER
RESET
*Pulse must be applied for cascading by 16 N bits.
Dimensions in parenthesis are in millimeters and are derived from the basic
inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION:
Thickness: 11k
Å
− 14kÅ, AL.
PASSIVATION:
10.4kÅ - 15.6k
Å, Silane
BOND PADS:
0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches


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