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CD4520BMS 데이터시트(PDF) 1 Page - Intersil Corporation |
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CD4520BMS 데이터시트(HTML) 1 Page - Intersil Corporation |
1 / 10 page 7-1206 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 December 1992 CD4518BMS, CD4520BMS CMOS Dual Up Counters Features • High Voltage Types (20V Rating) • CD4518BMS Dual BCD Up Counter • CD4520BMS Dual Binary Up Counter • Medium Speed Operation - 6MHz Typical Clock Frequency at 10V • Positive or Negative Edge Triggering • Synchronous Internal Carry Propagation • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Multistage Synchronous Counting • Multistage Ripple Counting • Frequency Dividers Description CD4518BMS Dual BCD Up Counter and CD4520BMS Dual Binary Up Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connect- ing Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. The CD4518BMS and CD4520BMS are supplied in these 16-lead outline packages: Braze Seal DIP H4S Frit Seal DIP H1F Ceramic Flatpack *H6P †H6W *CD4518B Only †CD4520B Only File Number 3342 Pinout CD4518BMS, CD4520BMS TOP VIEW Functional Diagram 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CLOCK A ENABLE A Q1A Q2A Q3A Q4A VSS RESET A VDD Q4B Q3B Q2B Q1B ENABLE B CLOCK B RESET B VSS = 8 VDD = 16 ÷10/÷16 C R 14 5 6 Q1A Q2A Q3A Q4A RESET A 7 2 CLOCK A ENABLE A ÷10/÷16 C R 912 13 14 Q1B Q2B Q3B Q4B RESET B 15 10 CLOCK B ENABLE B 3 11 |
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