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AD9225 데이터시트(PDF) 8 Page - Analog Devices |
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AD9225 데이터시트(HTML) 8 Page - Analog Devices |
8 / 25 page –8– AD9225 INTRODUCTION The AD9225 is a high performance, complete single-supply 12-bit ADC. The analog input range of the AD9225 is highly flexible, allowing for both single-ended or differential inputs of varying amplitudes that can be ac-coupled or dc-coupled. The AD9225 utilizes a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the differ- ence between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9225 can be configured to interface with 5 V or 3.3 V logic families. The AD9225 uses both edges of the clock in its internal timing circuitry (see Figure 1 and Specifications tables for exact timing requirements). The ADC samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time it is in hold mode. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized. ANALOG INPUT AND REFERENCE OVERVIEW Figure 2 is a simplified model of the AD9225. It highlights the relationship between the analog inputs, VINA and VINB, and the reference voltage, VREF. Like the voltage applied to the top of the resistor ladder in a flash ADC, the value VREF defines the maximum input voltage to the ADC core. The minimum input voltage to the ADC core is automatically defined to be –VREF. VCORE VINA VINB +VREF –VREF ADC CORE 12 AD9225 Figure 2. Equivalent Functional Input Circuit The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config- ure the inputs for either single-ended operation or differential operation. The A/D converter’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the ADC core is the difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation VCORE = VINA – VINB (1) defines the output of the differential input stage and provides the input to the ADC core. The voltage, VCORE, must satisfy the condition –VREF £ VCORE £ VREF (2) where VREF is the voltage at the VREF pin. While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9225. The power supplies bound the valid operating range for VINA and VINB. The condition AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) AVSS – 0.3 V < VINB < AVDD + 0.3 V where AVSS is nominally 0 V and AVDD is nominally 5 V, defines this requirement. The range of valid inputs for VINA and VINB is any combination that satisfies both Equations 2 and 3. For additional information showing the relationships among VINA, VINB, VREF, and the digital output of the AD9225, see Table IV. Refer to Table I and Table II at the end of this section for a sum- mary of the various analog input and reference configurations. ANALOG INPUT OPERATION Figure 3 shows the equivalent analog input of the AD9225, which consists of a differential sample-and-hold amplifier. The differential input structure of the SHA is highly flexible, allow- ing the devices to be easily configured for either a differential or single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single-supply or dual-supply systems. Also, note that the analog inputs, VINA and VINB, are interchangeable, with the exception that revers- ing the inputs to the VINA and VINB pins results in a polarity inversion. CS QS1 QH1 VINA VINB CS QS1 CPIN– CPAR CPIN+ CPAR QS2 CH QS2 CH Figure 3. Simplified Input Circuit The AD9225 has a wide input range. The input peaks may be moved to AVDD or AVSS before performance is compromised. This allows for much greater flexibility when selecting single- ended drive schemes. Op amps and ac coupling clamps can be set to available reference levels rather than be dictated according to what the ADC needs. Rev. C |
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