AD9389B

Rev. 0 | Page 7 of 12

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

LFCSP

LQFP

2, 39 to 47,

50 to 63

2, 50 to 58,

65 to 78

D[23:0]

I

Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from

1.8 V to 3.3 V.

6

6

CLK

I

Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

3

3

DE

I

Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.

4

4

HSYNC

I

Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

5

5

VSYNC

I

Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

18

23

EXT_SWG

I

Set Internal Reference Currents. Place 887 Ω resistor (1% tolerance) between this pin

and ground.

20

25

HPD

I

Hot Plug Detect Signal. This indicates to the interface whether the receiver is

connected. 1.8 V to 5.0 V CMOS logic levels.

7

7

S/PDIF

I

S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a

Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.

8

8

MCLK

I

9 to 12

9 to 12

I

13

13

SCLK

I

14

14

LRCLK

I

Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.

262

332

PD/A0

I

are set by the PD/A0 pin state when the supplies are applied to the AD9389B. 1.8 V

to 3.3 V CMOS logic levels.

21, 22

27, 28

TxC−/TxC+

O

Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic

level.

30, 31

37, 38

Tx2−/Tx2+

O

Differential Output Channel 2. Differential output of the red data at 10× the pixel

clock rate; TMDS logic level.

27, 28

34, 35

Tx1−/Tx1+

O

Differential Output Channel 1. Differential output of the green data at 10× the pixel

clock rate; TMDS logic level.

24, 25

30, 31

Tx0−/Tx0+

O

Differential Output Channel 0. Differential output of the blue data at 10× the pixel

clock rate; TMDS logic level.

32

40

INT

O

Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is

recommended. Active Low.

19, 23, 29

24, 29, 36,

41

AVDD

P

1.8 V Power Supply for TMDS Outputs.

1, 48, 49

1, 61 to 64

DVDD

P

1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the

digital logic and I/Os. They should be filtered and as quiet as possible.

15, 16, 17

16, 19 to 21

PVDD

P

1.8 V PLL Power Supply. The most sensitive portion of the AD9389B is the clock

generation circuitry. These pins provide power to the clock PLL. Provide quiet,

noise-free power to these pins.

N/A

15, 17, 18,

22, 26, 32,

39, 42, 43,

59, 60, 79,

80

GND

P

Ground. The ground return for all circuitry on-chip. It is recommended that the

AD9389B be assembled on a single, solid ground plane with careful attention given

to ground current paths.

64, paddle on

bottom side

N/A

DGND

Ground. The ground return for all circuitry on-chip. It is recommended that the

AD9389B be assembled on a single, solid ground plane with careful attention given

to ground current paths.

36

47

SDA

C3

Serial Port Data I/O. This pin serves as the serial port data I/O slave for register

access. Supports CMOS logic levels from 1.8 V to 3.3 V.

35

46

SCL

C3

Serial Port Data Clock. This pin serves as the serial port data clock slave for register

access. Supports CMOS logic levels from 1.8 V to 3.3 V.

37

48

MDA

C3

Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from

1.8 V to 3.3 V.

38

49

MCL

C3

Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels

from 1.8 V to 3.3 V.