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AD73322L 데이터시트(PDF) 11 Page - Analog Devices

부품명 AD73322L
상세설명  Low Cost, Low Power CMOS General-Purpose Dual Analog Front End
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AD73322L
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Mnemonic
Function
SCLK
Serial Clock Output. This rate determines the serial transfer rate to/from the codec. It is used to clock data or control
information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK)
divided by an integer number—this integer number being the product of the external master clock rate divider and the serial
clock rate divider.
MCLK
Master Clock Input. MCLK is driven from an external clock signal.
SDO
Serial Data Output. Both data and control information may be output on this pin and are clocked on the positive edge of
SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
SDOFS
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period before the first
bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low.
SDIFS
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period before the first bit
(MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low.
SDI
Serial Data Input. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK.
SDI is ignored when SE is low.
SE
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are
three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is
brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however,
the timing counters and other internal registers are at their reset values.
AGND1
Analog Ground/Substrate Connection.
AVDD1
Analog Power Supply Connection.
VOUTP2
Analog Output from the Positive Terminal of Output Channel 2.
VOUTN2
Analog Output from the Negative Terminal of Output Channel 2.
VOUTP1
Analog Output from the Positive Terminal of Output Channel 1.
VOUTN1
Analog Output from the Negative Terminal of Output Channel 1.
VINP2
Analog Input to the inverting input amplifier on Channel 2’s positive input.
VFBP2
Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input amplifiers are
bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator.
VINN2
Analog Input to the inverting input amplifier on Channel 2’s negative input.
VFBN2
Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input amplifiers are
bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator.


유사한 부품 번호 - AD73322L_15

제조업체부품명데이터시트상세설명
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유사한 설명 - AD73322L_15

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